Patents by Inventor Yeow Lim

Yeow Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140586
    Abstract: A system for sorting a number of dies from a wafer is provided. The system includes a first wafer table for holding a first wafer frame having the plurality of dies, wherein the first wafer table is inclined at a first angle with respect to a horizontal plane; a second wafer table to accept a plurality of dies, wherein the second wafer table is placed parallel to the horizontal plane; and a rotary turret having a plurality of heads to simultaneously pick, retain and place dies, and is positioned between the first wafer table and the second wafer table, wherein the rotary turret is inclined at a second angle with respect to the horizontal plane. Further, a process for sorting a number of dies from the wafer is also provided.
    Type: Application
    Filed: September 10, 2021
    Publication date: May 1, 2025
    Applicant: MIT SEMICONDUCTOR (TIAN JIN) CO., LTD.
    Inventors: Kim Mone KWONG, Siong Huat NEO, Kok Yeow LIM, Zhi Qiang MAO
  • Patent number: 10715790
    Abstract: The present invention includes a system and method for three-dimensional imaging and analysis of electronic components. Specifically, it permits rapid and reliable inspection of the lead foot angle in integrated circuit packages. A first image capturing device, a second image capturing device and a third image capturing device are arranged in a “corner shape” or “L-shape.” The first image capturing device forms the corner and obtains an image of the bottom of the component. The perspective viewing angle of the second image capturing device and the perspective viewing angle of the third image capturing device are orthogonal to each other to allow accurate three-dimensional reconstruction of the lead angles and detection of flaws or bends.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: July 14, 2020
    Assignee: GENERIC POWER PTE LTD
    Inventors: Hak Wee Tang, Ruini Cao, Kok Yeow Lim, Zin Oo Thant
  • Patent number: 10699923
    Abstract: The present invention includes a transfer system for flipping and checking electronic devices. A first rotary device has a plurality of transfer heads configured to pick electronic devices from a wafer table and place the electronic devices on a transfer head of a second rotary device. Check stations can be positioned around the first and second rotary devices and configured to inspect or check the electronic devices during the flipping process. The transfer system can further include an imaging device to inspect the accuracy of picking and placing of the electronic devices during the flipping process. The wafer table and the first rotary device are inclined to increase the operation space. The system accurately picks, flips and transfers chips at a high operation speed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 30, 2020
    Assignee: MIT SEMICONDUCTOR PTE LTD
    Inventors: Siong Huat Neo, Kim Mone Kwong, Kok Yeow Lim, Zhi Qiang Mao
  • Patent number: 10403782
    Abstract: A method for laser scribing of thin-films for the manufacture of solar cell panels comprises loading a workpiece with the transparent substrate facing downwards in an input station of a first machine; biasing a reference edge of the workpiece against a front and rear stopper associated with a linear drive; translating the workpiece back and forth between the input station and output station and firing two or more laser beams at a first frequency substantially vertically through a space between the input and output stations to pass through the transparent substrate of the workpiece to scribe parallel lines on the front electrodes with reference to the edge of the workpiece in contact with the front and rear stoppers; and indexing the two or more laser sources and repeating the back and forth translation of the work piece between the input and output stations.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: September 3, 2019
    Assignee: Manufacturing Integration Technology Ltd
    Inventors: Kim Mone Kwong, Teck Keong Boh, Kok Yeow Lim, Han Yong Lam
  • Publication number: 20190139795
    Abstract: The present invention includes a transfer system for flipping and checking electronic devices. A first rotary device has a plurality of transfer heads configured to pick electronic devices from a wafer table and place the electronic devices on a transfer head of a second rotary device. Check stations can be positioned around the first and second rotary devices and configured to inspect or check the electronic devices during the flipping process. The transfer system can further include an imaging device to inspect the accuracy of picking and placing of the electronic devices during the flipping process. The wafer table and the first rotary device are inclined to increase the operation space. The system accurately picks, flips and transfers chips at a high operation speed.
    Type: Application
    Filed: April 27, 2016
    Publication date: May 9, 2019
    Applicant: MIT SEMICONDUCTOR PTE LTD
    Inventors: Siong Huat NEO, Kim Mone KWONG, Kok Yeow LIM, Zhi Qiang MAO
  • Publication number: 20180324409
    Abstract: The present invention includes a system and method for three-dimensional imaging and analysis of electronic components. Specifically, it permits rapid and reliable inspection of the lead foot angle in integrated circuit packages. A first image capturing device, a second image capturing device and a third image capturing device are arranged in a “corner shape” or “L-shape.” The first image capturing device forms the corner and obtains an image of the bottom of the component. The perspective viewing angle of the second image capturing device and the perspective viewing angle of the third image capturing device are orthogonal to each other to allow accurate three-dimensional reconstruction of the lead angles and detection of flaws or bends.
    Type: Application
    Filed: May 2, 2017
    Publication date: November 8, 2018
    Inventors: Hak Wee TANG, Ruini CAO, Kok Yeow LIM, Zin Oo THANT
  • Patent number: 9929036
    Abstract: A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 27, 2018
    Assignee: MANUFACTURING INTEGRATION TECHNOLOGY LTD
    Inventors: Kim Mone Kwong, Kok Yeow Lim, Zhiqiang Mao
  • Publication number: 20170229604
    Abstract: The present invention describes an apparatus for a first laser scribing (P1) on the front electrode of a thin film solar cell panel and a similar apparatus for subsequent laser scribing (P2,P3) on the semiconductor layer and semiconductor layer/rear electrode. Before starting scribing process (P1), the left hand edge or reference line on the left hand edge on a workpiece is aligned substantively parallel to the linear drive before translating the workpiece on the apparatus. Similarly, the first and second scribed lines (Lp1,Lp2) formed during the P1 and P2 processes are separately aligned parallel to the linear drive before starting the relevant process (P2,P3). Alternatively, parallelism of the workpiece is carried out for each batch of the workpiece. In both apparatuses, the laser sources are mounted on independently motorised axes.
    Type: Application
    Filed: February 14, 2017
    Publication date: August 10, 2017
    Inventors: Kim Mone KWONG, Teck Keong Boh, Kok Yeow Lim, Han Yong Lam
  • Publication number: 20170133259
    Abstract: A system and method for peeling a semiconductor chip from a tape using a multistage ejector is disclosed. A housing in the multistage ejector houses a plural sets of tape removing contacts. A pick and place unit is moved slowly to have contact with the chip. A vacuum source is utilized for generating vacuum to suck the tape. Plural sets of contacts such as inner, middle and outer contacts are independently or together moved below the tape at various stages by utilizing their respective actuation mechanism. A controller can independently control the movements of each contact to effectively remove or loosen the tape from the chip. A pick and place unit can then pick up the chip easily without any damage to chip.
    Type: Application
    Filed: May 13, 2015
    Publication date: May 11, 2017
    Inventors: Kim Mone KWONG, Kok Yeow LIM, Zhiqiang MAO
  • Publication number: 20120181259
    Abstract: The present invention describes an apparatus (100) for a first laser scribing (P1) on the front electrode of a thin film solar cell panel and a similar apparatus (100a) for subsequent laser scribing (P2, P3) on the semiconductor layer and semiconductor layer/rear electrode. Before starting scribing process P1, the left hand edge or reference line on the left hand edge on a workpiece is aligned substantively parallel to the linear drive (140) before translating the workpiece on the apparatus (100). Similarly, the first and second scribed lines (Lp1, Lp2) formed during the P1 and P2 processes are separately aligned parallel to the linear drive (140) before starting the relevant process (P2, P3). Alternatively, parallelism of the workpiece is carried out for each batch of the workpiece. In both apparatuses (100, 100a), the laser sources (150) are mounted on independently motorized axes.
    Type: Application
    Filed: October 7, 2009
    Publication date: July 19, 2012
    Applicant: Manufacturing Integration Technology Ltd.
    Inventors: Kim Mone Kwong, Teck Keong Boh, Kok Yeow Lim, Han Yong Lam
  • Patent number: 7692440
    Abstract: A water jet handler (200) has a loading location (205), a cutting location (210), and an unloading location (215); and two movable mounts (240 and a 245). As a first movable mount (240) receives a molded substrate at the loading location (205), and transports it to the cutting location (210), a second movable mount (245) transports singulated semiconductor packages of a previously singulated molded substrate from the cutting location (210) to the unloading location (215). As the molded substrate on the first movable mount (240) is cut in the X direction (232) by a water jet, the singulated semiconductor packages are unloaded. The molded substrate is then transferred to the second movable mount (245) on which it is cut in the Y direction (272) to produce singulated semiconductor packages, as the first movable mount (240) returns to the loading location (205), when another molded substrate is loaded.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 6, 2010
    Assignee: Advanced Systems Automation Limited
    Inventors: Jimmy Hwee Seng Chew, Kok Yeow Lim, Fulin Liu
  • Publication number: 20080299098
    Abstract: The present invention demonstrated the potential use of Lactobacillus johnsonii D115 as a probiotic, as a prophylactic agent or as a surface treatment of materials against human and animal pathogens such as Brachyspira pilosicoli, Brachyspira hyodysenteriae, Shigella sonnei, Vibrio cholera, Vibrio parahaemolyticus, Campylobacter jejuni, Streptococcus pneumoniae, Enterococcus faecalis, Enterococcus faecium, Clostridium perfringens, Yersinia enterocolitica, Escherichia coli, Klebbsiella pneumoniae, Staphylococcus aureus, Salmonella spp., Bacillus cereus, Aspergillus niger and Fusarium chlamydosporum. The proteineous antimicrobial compound was partially characterized and found to be heat tolerant up to 121° C. for 15 min, and acid tolerant up to pH1 for 30 min at 40° C. The compound is also stable to enzymatic digestion, being able to retain more than 60% antimicrobial activity when treated with pepsin and trypsin.
    Type: Application
    Filed: April 24, 2008
    Publication date: December 4, 2008
    Inventors: Chea-Yun Se, Fui-Fong Yong, Hai-Meng Tan, Wee Ming Yeo, Alex Yeow-Lim Teo
  • Publication number: 20070196979
    Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Applicant: Advanpack Solutions Pte Ltd
    Inventors: Teck Tan, Hwee Seng Chew, Kok Yeow Lim, Abd. Razak Chichik, Kee Lau, Chuan Wong
  • Patent number: 7247299
    Abstract: Antimicrobial compounds from Bacillus subtilis for use against animal and human pathogens. A novel strain of Bacillus subtilis was isolated from the gastrointestinal tract of poultry and was found to produce a factor or factors that have excellent inhibitory effects on Clostridium perfringens, Clostridium difficile, Campylobacter jejuni, Campylobacter coli, and Streptococcus pneumoniae. The factor(s) retain full viability and antimicrobial activity after heat treatment. The invention provides a method of treatment of pathogenic microorganisms including C. perfringens.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: July 24, 2007
    Assignee: Kemin Industries, Inc.
    Inventors: Angeline Seah Huay Lin, Alex Yeow-Lim Teo, Tan Hai Meng
  • Publication number: 20070111522
    Abstract: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.
    Type: Application
    Filed: November 12, 2005
    Publication date: May 17, 2007
    Inventors: Yeow Lim, Wei Lu, Liang Hsia, Jyoti Gupta, Chim Seet, Hao Zhang
  • Publication number: 20070075371
    Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
    Type: Application
    Filed: August 21, 2006
    Publication date: April 5, 2007
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Yeow Lim, Randall Cha, Alex See, Wang Goh
  • Publication number: 20060094339
    Abstract: A water jet handler (200) has a loading location (205), a cutting location (210), and an unloading location (215); and two movable mounts (240 and a 245). As a first movable mount (240) receives a molded substrate at the loading location (205), and transport it to the cutting location (210), a second movable mount (245) transports singulated semiconductor packages of a previously singulated molded substrate from the cutting location (210) to the unloading location (215). As the molded substrate on the first movable mount (240) is cut in the X direction (232) by a water jet, the singulated semiconductor packages are unloaded. The molded substrate is then transferred to the second movable mount (245) on which it is cut in the Y direction (272) to produce singulated semiconductor packages, as the first movable mount (240) returns to the loading location (205), when another molded substrate is loaded.
    Type: Application
    Filed: August 29, 2003
    Publication date: May 4, 2006
    Inventors: Jimmy Hwee Chew, Kok Yeow Lim, Fulin Liu
  • Publication number: 20060040491
    Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
    Type: Application
    Filed: August 21, 2004
    Publication date: February 23, 2006
    Inventors: Yeow Lim, Alex See, Tae Lee, David Vigar, Liang Hsia, Kin Pey
  • Publication number: 20060003573
    Abstract: An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 5, 2006
    Inventors: Yeow Lim, Wuping Liu, Tae Lee, Bei Zhang, Juan Boon Tan, Alan Cuthbertson, Chin Neo
  • Publication number: 20050090095
    Abstract: A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A structure having a metal structure formed thereover is provided. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. The upper dielectric layer is patterned to form an opening exposing a portion of the underlying middle dielectric material layer. The opening having a width. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. The middle dielectric material layer opening exposing a portion of the middle etch stop layer.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Inventors: Yeow Lim, Wuping Liu, Tae Lee, Bei Zhang, Juan Tan, Alan Cuthbertson, Chin Neo