Patents by Inventor Yervant D. Lepejian
Yervant D. Lepejian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7174341Abstract: A dynamic database management system includes a data dictionary, a data importer and a query front-end. The data importer automatically imports data from an input file into a database, while adding new tables for new attributes as necessary, and updating parameters and folders tables in the data dictionary accordingly, so that end-users may access the imported data by database queries through the query front-end.Type: GrantFiled: May 31, 2001Date of Patent: February 6, 2007Assignee: Synopsys, Inc.Inventors: Hovhannes Ghukasyan, Suren Chilingaryan, Yervant D. Lepejian
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Patent number: 6966049Abstract: A software development tool employing workflows for developing user interactive programs is described. The tool includes means for displaying a workspace on a computer screen, and means for displaying objects on the computer screen that are individually selectable to be placed and coupled together in the workspace to define a workflow for a user interactive program. Several objects have interactively alterable operation parameters. One object performs an interactively alterable switch function for directing data flow within the workflow. Another object facilitates branch processing according to a user indicated selection from displayed information generated by the user interactive program. Another object facilitates assigning a name to an input port of another object so that data may be directly provided to that input port. Another object prompts a user for input when a condition is met while executing the user interactive program.Type: GrantFiled: April 24, 2001Date of Patent: November 15, 2005Assignee: Heuristics Physics Laboratories, Inc.Inventors: Yervant D. Lepejian, Gurgen Lachinian, Hovhannes Ghukasyan, Arman Sagatelian
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Patent number: 6920596Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.Type: GrantFiled: January 22, 2002Date of Patent: July 19, 2005Assignee: Heuristics Physics Laboratories, Inc.Inventors: Arman Sagatelian, Alvin Jee, Julie Segal, Yervant D. Lepejian, John M. Caywood
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Publication number: 20040015841Abstract: A software development tool employing workflows for developing user interactive programs is described. The tool includes means for displaying a workspace on a computer screen, and means for displaying objects on the computer screen that are individually selectable to be placed and coupled together in the workspace to define a workflow for a user interactive program. Several objects have interactively alterable operation parameters. One object performs an interactively alterable switch function for directing data flow within the workflow. Another object facilitates branch processing according to a user indicated selection from displayed information generated by the user interactive program. Another object facilitates assigning a name to an input port of another object so that data may be directly provided to that input port. Another object prompts a user for input when a condition is met while executing the user interactive program.Type: ApplicationFiled: April 24, 2001Publication date: January 22, 2004Inventors: Yervant D. Lepejian, Gurgen Lachinian, Hovhannes Ghukasyan, Arman Sagatelian
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Publication number: 20030198375Abstract: A method for reducing data storage requirements for defects identified on one or more related semiconductor wafers is described. The method includes: receiving images of one or more related semiconductor wafers; identifying defects on the one or more related semiconductor wafers by comparing the received images with corresponding images of a model semiconductor wafer having an identical integrated circuit design as the one or more related semiconductor wafers; and compressing information of the identified defects for data storage.Type: ApplicationFiled: April 17, 2002Publication date: October 23, 2003Inventor: Yervant D. Lepejian
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Publication number: 20030187848Abstract: A method and apparatus for restricted access to a database according to user permissions are described. A user permissions file residing on a server includes information of permissions related to database records, and which of those permissions are associated with individual users. A permissions manager also residing on the server manages user queries either directly by generating restricted queries that reflect only authorized access to database records for the user generating the query, or indirectly by downloading a permissions filter or information for a restricted parameters screen to the user's client, so as to generate the restricted query on the client. In any case, a database management system residing on the server receives the restricted query and generates a result by accessing only authorized database records for the user, and communicates the result back to the user's client.Type: ApplicationFiled: April 2, 2002Publication date: October 2, 2003Inventors: Hovhannes Ghukasyan, Yervant D. Lepejian
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Publication number: 20030140294Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.Type: ApplicationFiled: January 22, 2002Publication date: July 24, 2003Inventors: Arman Sagatelian, Alvin Jee, Julie Segal, Yervant D. Lepejian, John M. Caywood
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Publication number: 20020184228Abstract: A dynamic database management system includes a data dictionary, a data importer and a query front-end. The data importer automatically imports data from an input file into a database, while adding new tables for new attributes as necessary, and updating parameters and folders tables in the data dictionary accordingly, so that end-users may access the imported data by database queries through the query front-end.Type: ApplicationFiled: May 31, 2001Publication date: December 5, 2002Inventors: Hovhannes Ghukasyan, Suren Chilingaryan, Yervant D. Lepejian
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Publication number: 20020154119Abstract: An apparatus and method are described for performing branch processing according to a user indicated selection from displayed graphics. A chart engine in a workflow receives a data file having a header followed by data. The header includes parameters and branch processing information. The chart engine generates graphics data from the received data according to the parameters information, and an output engine stores the graphics data in a data file along with the original header information. The graphics data is readable by a viewer that displays graphics generated from the graphics data on a computer display. When the user indicates a selection from the displayed graphics, the viewer detects the user indicated selection, reads the branch processing information from the header of the data file, and performs branch processing according to the user indicated selection.Type: ApplicationFiled: April 24, 2001Publication date: October 24, 2002Inventors: Yervant D. Lepejian, Gurgen Lachinian, Rafik Marutyan
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Patent number: 6092030Abstract: Apparatus for supplying a signal after a predetermined time delay comprises circuitry for generating a base delay signal that is synchronized to a stable master oscillator insensitive to changes in at least one environmental variable. A vernier signal delay circuit provides delay increments smaller than those available from the base delay signal, the delay increments being sensitive to said at least one environmental variable. Storage circuitry is provided for storing information related to the duration of the delay increments as function of at least one environmental variable for which correction is to be supplied. Sensing circuitry is provided for sensing the at least one environmental variable for which correction is to be provided to supply a sensed at least one environmental variable.Type: GrantFiled: April 2, 1997Date of Patent: July 18, 2000Assignee: Credence Systems CorporationInventors: Yervant D. Lepejian, Lawrence A. Kraus, Julie D. Segal, John M. Caywood
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Patent number: 5956350Abstract: A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation.Type: GrantFiled: October 27, 1997Date of Patent: September 21, 1999Assignees: LSI Logic Corporation, Heuristic Physics Laboratories, Inc.Inventors: V. Swamy Irrinki, Yervant D. Lepejian
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Patent number: 5822228Abstract: A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear.Type: GrantFiled: May 27, 1997Date of Patent: October 13, 1998Assignees: LSI Logic Corporation, Heuristic Physics Laboratories, Inc.Inventors: V. Swamy Irrinki, Yervant D. Lepejian
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Patent number: 5475695Abstract: An automated system for identification of fabrication defects that lead to the failure of IC products. Design information of the product to be tested is analyzed to identify electrical node-to-node faults that can be caused by fabrication defects. The circuit is then analyzed to determine the electrical response to input patterns which result from the node-to-node faults. A matrix which relates failure responses to a multiplicity of input patterns as a function of process defects is constructed. This response matrix is used to identify the fabrication defect. In those cases in which the response matrix is degenerate, i.e. a set of output responses can arise from more than one fault, knowledge about the probability of occurrence of various defects is used to assign probabilities to the node-to-node faults which may generate the output response set. The system then takes knowledge of a specific IC test system and the response matrix to generate a set of test vectors to analyze a product.Type: GrantFiled: March 19, 1993Date of Patent: December 12, 1995Assignee: Semiconductor Diagnosis & Test CorporationInventors: John M. Caywood, Alan B. Helffrich, III, Yervant D. Lepejian