Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.