Abstract: Methods and systems for on-die measuring jitter of a clock under test are presented. In an aspect, an apparatus comprises a delay line having a plurality of delay elements, the outputs of which are sampled at the expected transition time of the clock under test. The sampled outputs are provided to an edge detector that indicates the presence of the clock transition at a specific time, and a latching circuit stores a record of all the edge locations seen during a sampling window. In some aspects, a counting circuit counts and stores how many times the transition occurs at each specific time during the sampling window. The counts stored by the counting circuit provide histogram data that can be analyzed to determine the jitter characteristics of the clock under test.

Abstract: Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.

Abstract: Methods and systems for on-die measuring jitter of a clock under test are presented. In an aspect, an apparatus comprises a delay line having a plurality of delay elements, the outputs of which are sampled at the expected transition time of the clock under test. The sampled outputs are provided to an edge detector that indicates the presence of the clock transition at a specific time, and a latching circuit stores a record of all the edge locations seen during a sampling window. In some aspects, a counting circuit counts and stores how many times the transition occurs at each specific time during the sampling window. The counts stored by the counting circuit provide histogram data that can be analyzed to determine the jitter characteristics of the clock under test.

Abstract: A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.

Abstract: In a particular implementation, an apparatus to stabilize a supply voltage includes a first current source, a second current source, and a control circuit. The first current source is responsive to a detection signal and has an output coupled to a voltage regulator circuit via an output node. The second current source is also coupled to the output node. The control circuit includes an input responsive to the detection signal and an output coupled to the second current source. The control circuit is configured to enable the second current source based on a delayed version of the detection signal.

Abstract: A power on reset circuit including an inverter powered by a first power domain, the inverter including a data input coupled to a power rail of a second power domain; logic circuitry coupled with an output of the inverter, the logic circuitry having a control signal output; and wherein, during a power up operation, the first power domain powers up before the second power domain powers up. Upon power up of the first power domain, the inverter can output a high signal to the logic circuitry and output a low signal to the logic circuitry in response to power up of the second power domain. The logic circuitry is further configured to output a first value for a control signal in response to the first power domain powering up and configured to output a second value for the control signal in response to the second power domain powering up.

Abstract: In a particular implementation, an apparatus to stabilize a supply voltage includes a first current source, a second current source, and a control circuit. The first current source is responsive to a detection signal and has an output coupled to a voltage regulator circuit via an output node. The second current source is also coupled to the output node. The control circuit includes an input responsive to the detection signal and an output coupled to the second current source. The control circuit is configured to enable the second current source based on a delayed version of the detection signal.

Abstract: A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.

Abstract: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.