Patents by Inventor Yeshwanth Kumar Mallavajula

Yeshwanth Kumar Mallavajula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for data level shifting with boost assisted inputs for high speed and low voltage applications
    Patent number: 10128846
    Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yeshwanth Kumar Mallavajula, Wilson Chen, Chiew-Guan Tan
  • APPARATUS AND METHOD FOR DATA LEVEL SHIFTING WITH BOOST ASSISTED INPUTS FOR HIGH SPEED AND LOW VOLTAGE APPLICATIONS
    Publication number: 20180287609
    Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 4, 2018
    Inventors: Yeshwanth Kumar Mallavajula, Wilson Chen, Chiew-Guan Tan