Patents by Inventor Yeu-Der Chih

Yeu-Der Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
    Patent number: 7269063
    Abstract: Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Yeu-Der Chih
  • Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
    Publication number: 20060221682
    Abstract: Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
    Type: Application
    Filed: May 12, 2006
    Publication date: October 5, 2006
    Inventor: Yeu-Der Chih
  • Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm
    Patent number: 7072215
    Abstract: Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: July 4, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Yeu-Der Chih
  • Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm
    Publication number: 20050185464
    Abstract: Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
    Type: Application
    Filed: February 24, 2004
    Publication date: August 25, 2005
    Inventor: Yeu-Der Chih