Patents by Inventor Yeul Na

Yeul Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230019977
    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
    Type: Application
    Filed: March 1, 2022
    Publication date: January 19, 2023
    Inventors: Jae Hyung LEE, Yeul NA, Youngsik KIM, Woo-Shik JUNG
  • Publication number: 20220292276
    Abstract: A method performed at an electronic device with one or more processors and memory storing one or more programs includes receiving a plurality of images of a machine readable code. A respective image of the plurality of images corresponds to a distinct wavelength. The method also includes analyzing the respective image of the plurality of images to obtain a respective processed information; combining the respective processed information to obtain combined information; and providing the combined information to at least one program of the one or more programs stored in the memory for processing.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 15, 2022
    Inventors: Jae Hyung LEE, Su Ryeo OH, Yeul NA, Se Jin PARK, Youngsik KIM, Wongyun CHOE, Il-hoon CHOI, Bomjoon SEO, Sunghyun JOO, Hwasup SHIN, Minsoo CHO
  • Patent number: 11264418
    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 1, 2022
    Assignee: Stratio Inc.
    Inventors: Jae Hyung Lee, Yeul Na, Youngsik Kim, Woo-Shik Jung
  • Publication number: 20200256731
    Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Jae Hyung LEE, Youngsik KIM, Yeul NA, Juhyung KANG
  • Patent number: 10600640
    Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 24, 2020
    Assignee: Stratio, Inc.
    Inventors: Woo-Shik Jung, Yeul Na, Youngsik Kim, Jae Hyung Lee, Jin Hyung Lee
  • Patent number: 10366884
    Abstract: A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than, the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 30, 2019
    Assignee: STRATIO
    Inventors: Jaehyung Lee, Yeul Na, Youngsik Kim
  • Publication number: 20190221595
    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
    Type: Application
    Filed: October 22, 2018
    Publication date: July 18, 2019
    Inventors: Jae Hyung LEE, Yeul NA, Youngsik KIM, Woo-Shik JUNG
  • Patent number: 10281327
    Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: May 7, 2019
    Assignee: STRATIO
    Inventors: Jae Hyung Lee, Youngsik Kim, Yeul Na, Juhyung Kang
  • Patent number: 10109662
    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 23, 2018
    Assignee: Stratio, Inc.
    Inventors: Jae Hyung Lee, Yeul Na, Youngsik Kim, Woo-Shik Jung
  • Publication number: 20180094976
    Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Jae Hyung LEE, Youngsik Kim, Yeul Na, Juhyung Kang
  • Publication number: 20170287706
    Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing.
    Type: Application
    Filed: June 15, 2017
    Publication date: October 5, 2017
    Inventors: Woo-Shik Jung, Yeul Na, Youngsik Kim, Jae Hyung Lee, Jin Hyung Lee
  • Publication number: 20170195327
    Abstract: A server system receives from a first electronic device a first device identifier and network information of the first electronic device; subsequent to receiving the first device identifier and the network information of the first electronic device, receives from a second electronic device a second device identifier and network information of the second electronic device; in response to receiving from the second electronic device the second device identifier and the network information of the second electronic device, determines whether the first device identifier is associated with the second device identifier; and, in accordance with a determination that the first device identifier is associated with the second device identifier, sends to the second electronic device the network information of the first electronic device and/or sends to the first electronic device the network information of the second electronic device.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Inventors: Jae Hyung LEE, Youngsik Kim, Yeul Na, Wooshik Jung, Seema Bhattiprolu
  • Patent number: 9378950
    Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 28, 2016
    Assignees: STRATIO, STRATIO INC.
    Inventors: Jae Hyung Lee, Youngsik Kim, Yeul Na, Woo-Shik Jung
  • Patent number: 9343608
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 17, 2016
    Assignee: Board of Regents, The University of Texas System
    Inventors: Yeul Na, Krishna C Saraswat
  • Publication number: 20160099372
    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Inventors: Jae Hyung Lee, Yeul Na, Youngsik Kim, Woo-Shik Jung
  • Publication number: 20140363917
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 11, 2014
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: YEUL NA, KRISHNA C. SARASWAT
  • Patent number: 8896083
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 25, 2014
    Assignee: Board of Regents, The University of Texas System
    Inventors: Yeul Na, Krishna C. Saraswat
  • Publication number: 20140264501
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR RESEARCH CORPORATION
    Inventors: Yeul Na, KRISHNA C. SARASWAT