Abstract: A systolic architecture for computing C+AB, AB, C+AB2 or AB over a class of GF(2m) free global connection, wherein the A, B and C are the input elements of the GF(2m). The systolic architecture includes an inner product unit and a modular unit. The inner product unit includes m2 pieces of U cells and 2m+1 pieces of latch units. Each U cell includes a AND gate, a repulsive (or XOR) gate and three latches. The coefficients Aj, Bj and C<2j> of A, B and C are respectively inputted via the input ends Aj, Sj and C<2j> of U0,j, wherein the <2j> represents 2j modulo m+1. The modular unit includes m XOR gates for computing the modular p(x).

Abstract: Discrete Fourier transformation is applied to an analog system so that a signal be transfering, the analog data can be corrected before being quantized and after being transferred and received. In the DFT cyclic decoder and the method of the same, a cyclic property of DFT code is used to induce a decoding way in the receiving end of a communication system. This way is used to design a basic decoding circuit and a fast decoding circuit structure. Since the decoding process is quick and the structure is simple so that the analog error correcting code is used widely.

Abstract: An integrated drive electronics (IDE) master-slave selector used in a computer system with at least one hard disk drive, for users to conveniently select one hard disk drive as a master hard disk drive. The IDE master-slave selector of this present invention is characterized as an intelligent IDE master-slave selector comprising a master slave selector consisting of a first mode, a second mode, a third mode and a fourth mode. The master slave selector is mounted at the rear vacant board of a PCI/ISA slot of a computer system, and the wirings of the master-slave selection of the hard disk drive are connected beforehand, thus enabling users to switch the selector and choose one of the master-slave operation modes of the hard disk drive.

Abstract: The present invention provides a turbo-code decoder that adopts the parallel and systolic array VLSI structure design. Since the output of previous level can be used as the input of next level. So the advantages of the parallel and the pipeline calculation are totally achieved. The latency is only N+M+2 units of time, the latency is shorten to as about ⅕ comparing to the conventional sequential calculation structure that takes 5*(N+M) units of time. The decoding throughput is about 5*(N+M) times higher than the conventional decoder. Although the quantity of the circuit gate is about 5*(N+M) times higher than the conventional decoder. However, the VLSI techniques had been progressively improved nowadays, thus the hardware complexity is easy to overcome. Devoting the hardware cost to get the higher speed will be a changeless trend.

Abstract: The present invention provides a turbo-code block message tailing method and the turbo-code encoder employing the same and having two recursive systematic convolution encoders. Each recursive systematic convolution encoder comprises M registers, counted from the input side nearest to the block message; the sequence is m0 register, m1, register, . . . , mM−1, register. After the related data of the block message sequentially had been input, the input of the register m0 is set and fastened to 0 by using the switch device, and sequentially outputs the data that are temporally stored in all registers, and makes the final state of all registers back to the 0 state. The present invention is applied in the short block length communication system. The error-correcting performance is manifestly excellent. Since the present invention dose not have to check the data temporally stored in the registers. Thus, the encoder structure is simple and regular.

Abstract: The present invention provides a fast turbo-code encoder. The advantage of the encoding device is the encoding data is output via less exclusive-or (XOR) gate operations. The structure of the fast turbo-code encoding directly applies the exclusive-or operation on the input data and the internal value of the register, the encoding output is obtained via less exclusive-or gate time. Thus, the device of the present invention saves half of the gate time comparing to the conventional structure.

Abstract: This invention provides a method of automatically adjusting interrupt frequency. The following steps are provided. First, a computer system is provided with an operating system able to deliver a plurality of interrupts with a first interrupt frequency. A counter is used to count a number of occurrences of the interrupt until the number reaches a predetermined number, and then the counter is reset to zero. The predetermined number is divided by the first interrupt frequency to obtain a product, and calculate an error between the product and an actual period of time elapsed for the predetermined number of interrupts is calculated. Lastly, the invention detects whether the error exceeds a predetermined range and adjusting the first interrupt frequency to limit the error within said predetermined range.