Patents by Inventor Yevgen Ryazanov

Yevgen Ryazanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10802852
    Abstract: According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a file. A database of register and memory values which represent the complete history of register and memory value changes during a simulation can be created from trace information and can be accessed to non-intrusively obtain any processor register or memory value during simulation. The processor register and memory values of the database can also be accessed to symbolically show the behavior of ESW concurrently with hardware behavior in the simulation.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: October 13, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Andrew R. Wilmot, Neeti Khullar Bhatnagar, Qizhang Chao, George Franklin Frazier, Yevgen Ryazanov
  • Patent number: 9400858
    Abstract: Essential information for system operations, memory analysis, and design signal analysis is captured while a hardware based verification platform is performing emulation and testing. This recorded information is then accessible via a memory device and can be used to perform offline debugging with a virtual verification machine (VVM). Users can then release the shared resources and run operation commands to control replay of the design test or emulation in offline mode. Users can access any point in time of the recorded emulation in order to perform detailed design analysis and debugging operations. Offline analysis and debugging may include running certain design cycles, rerunning the emulation until the design reaches a certain state, evaluating memory contents in the design, evaluating design signals for any node in the design, etc.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 26, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Tsair-Chin Lin, Jingbo Gao, Yevgen Ryazanov