Patents by Inventor Yevgeni Sabin
Yevgeni Sabin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418361Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11789516Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: GrantFiled: May 22, 2020Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11558158Abstract: A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.Type: GrantFiled: November 10, 2020Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Michael Shusterman, John Fallin, Ana M. Yepes, Dong-Ho Han, Nasser A. Kurd, Tomer Levy, Ehud Reshef, Arik Gihon, Ido Ouzieli, Yevgeni Sabin, Maor Tal, Zhongsheng Wang, Amit Zeevi
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Publication number: 20220179473Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: ApplicationFiled: May 22, 2020Publication date: June 9, 2022Applicant: Intel CorporationInventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Publication number: 20220150006Abstract: A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.Type: ApplicationFiled: November 10, 2020Publication date: May 12, 2022Inventors: Michael SHUSTERMAN, John FALLIN, Ana M. YEPES, Dong-Ho HAN, Nasser A. KURD, Tomer LEVY, Ehud RESHEF, Arik GIHON, Ido OUZIELI, Yevgeni SABIN, Maor TAL, Zhongsheng WANG, Amit ZEEVI
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Patent number: 11216276Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.Type: GrantFiled: December 27, 2018Date of Patent: January 4, 2022Assignee: Intel CorporationInventors: Eliezer Weissmann, Hisham Abu-Salah, Daniel Lederman, Nir Rosenzweig, Efraim Rotem, Esfir Natanzon, Yevgeni Sabin, Shay Levy
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Publication number: 20200210184Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Eliezer Weissmann, Hisham Abu-Salah, Daniel Lederman, Nir Rosenzweig, Efraim Rotem, Esfir Natanzon, Yevgeni Sabin, Shay Levy
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Patent number: 10372198Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.Type: GrantFiled: August 25, 2017Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
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Patent number: 10345889Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: GrantFiled: August 4, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20180120924Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: ApplicationFiled: August 4, 2017Publication date: May 3, 2018Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20170371400Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.Type: ApplicationFiled: August 25, 2017Publication date: December 28, 2017Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
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Patent number: 9760160Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.Type: GrantFiled: May 27, 2015Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
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Patent number: 9760158Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: GrantFiled: June 6, 2014Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Patent number: 9671853Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.Type: GrantFiled: September 12, 2014Date of Patent: June 6, 2017Assignee: Intel CorporationInventors: Yoni Aizik, Eliezer Weissmann, Efraim Rotem, Yevgeni Sabin, Doron Rajwan, Ahmad Yasin
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Publication number: 20160349828Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.Type: ApplicationFiled: May 27, 2015Publication date: December 1, 2016Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
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Publication number: 20160077569Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Yoni Aizik, Eliezer Weissmann, Efraim Rotem, Yevgeni Sabin, Doron Rajwan, Ahmad Yasin
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Publication number: 20150355705Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon