Patents by Inventor Yevgeniy Bak

Yevgeniy Bak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168888
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Application
    Filed: January 3, 2024
    Publication date: May 23, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy BAK, Mehmet IYIGUN, Jonathan E. LANGE
  • Publication number: 20240103876
    Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 28, 2024
    Inventors: Ishwar AGARWAL, George CHRYSOS, Oscar ROSELL MARTINEZ, Yevgeniy BAK
  • Patent number: 11907135
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: February 20, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Jonathan E. Lange
  • Patent number: 11860783
    Abstract: Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, Yevgeniy Bak, Lisa Ru-feng Hsu
  • Publication number: 20230409490
    Abstract: Ensuring data security when tiering volatile and non-volatile byte-addressable memory. A portion of cache data stored in a first memory that is byte-addressable and volatile is identified for copying to a second memory that is byte-addressable and non-volatile. The portion of cache data is associated with cryptographic requirements for storing the portion of cache data on non-volatile storage. Cryptographic capabilities of the second memory are identified. When each of the cryptographic requirements is met by the cryptographic capabilities, the portion of cache data is copied to the second memory while relying on the second memory to encrypt the portion of cache data. When at least one cryptographic requirement is not met by the cryptographic capabilities, the portion of cache data is encrypted to generate an encrypted portion of cache data, and the encrypted portion of cache data is copied to the second memory.
    Type: Application
    Filed: December 2, 2021
    Publication date: December 21, 2023
    Inventors: Yevgeniy BAK, Mehmet IYIGUN, Landy WANG
  • Patent number: 11847459
    Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: December 19, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, George Chrysos, Oscar Rosell Martinez, Yevgeniy Bak
  • Publication number: 20230325191
    Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 12, 2023
    Inventors: Ishwar AGARWAL, George CHRYSOS, Oscar ROSELL MARTINEZ, Yevgeniy BAK
  • Publication number: 20230289288
    Abstract: Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.
    Type: Application
    Filed: May 3, 2022
    Publication date: September 14, 2023
    Inventors: Ishwar AGARWAL, Yevgeniy BAK, Lisa Ru-feng HSU
  • Publication number: 20230259371
    Abstract: Dynamically overriding a function based on a capability set. A computer system reads a portion of an executable image file. The portion includes a first memory address corresponding to a first callee function implementation. The first memory address was inserted into the portion by a compiler toolchain. Based on extensible metadata included in the executable image file, and based on a capability set that is specific to the computer system, the computer system determines a second memory address corresponding to a second callee function implementation. Before execution of the portion, the computer system modifies the portion to replace the first memory address with the second memory address.
    Type: Application
    Filed: April 19, 2022
    Publication date: August 17, 2023
    Inventors: Pranav KANT, Joseph Norman BIALEK, Xiang FAN, YongKang ZHU, Gabriel Thomas Kodjo DOS REIS, Russell Bivens KELDORPH, Mehmet IYIGUN, Russell Charles HADLEY, Roy WILLIAMS, Kenneth Dean JOHNSON, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Yevgeniy BAK
  • Patent number: 11720374
    Abstract: Dynamically overriding a function based on a capability set. A computer system reads a portion of an executable image file. The portion includes a first memory address corresponding to a first callee function implementation. The first memory address was inserted into the portion by a compiler toolchain. Based on extensible metadata included in the executable image file, and based on a capability set that is specific to the computer system, the computer system determines a second memory address corresponding to a second callee function implementation. Before execution of the portion, the computer system modifies the portion to replace the first memory address with the second memory address.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: August 8, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pranav Kant, Joseph Norman Bialek, Xiang Fan, YongKang Zhu, Gabriel Thomas Kodjo Dos Reis, Russell Bivens Keldorph, Mehmet Iyigun, Russell Charles Hadley, Roy Williams, Kenneth Dean Johnson, Pedro Miguel Sequeira De Justo Teixeira, Yevgeniy Bak
  • Publication number: 20230185729
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table’s entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy BAK, Mehmet IYIGUN, Jonathan E. LANGE
  • Patent number: 11573906
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: February 7, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Jonathan E. Lange
  • Patent number: 11403092
    Abstract: Enacting a compliance action using an assessment that considers a mix of coldpatches and hotpatches includes identifying a policy defining the compliance condition based on patching status of a software component. A patching state of the software component is determined, including identifying evidence of coldpatched binary file(s) and hotpatch binary file(s) applicable to the software component, and using the evidence to determine whether or not the hotpatch binary file(s) have been applied to a memory image into which an instance of the software component is loaded. Based on the policy and on the patching state of the software component, a compliance action is enacted for the compliance condition. The compliance action includes generating a health report or a health attestation, initiating a patching action, initiating an execution control action, and the like.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 2, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Maxwell Christopher Renke, Benjamin M. Schultz, Yevgeniy Bak, Vijaykumar Sharma, Apurva Ashvinkumar Thanky, Hari R. Pulapaka
  • Publication number: 20220012044
    Abstract: Enacting a compliance action using an assessment that considers a mix of coldpatches and hotpatches includes identifying a policy defining the compliance condition based on patching status of a software component. A patching state of the software component is determined, including identifying evidence of coldpatched binary file(s) and hotpatch binary file(s) applicable to the software component, and using the evidence to determine whether or not the hotpatch binary file(s) have been applied to a memory image into which an instance of the software component is loaded. Based on the policy and on the patching state of the software component, a compliance action is enacted for the compliance condition. The compliance action includes generating a health report or a health attestation, initiating a patching action, initiating an execution control action, and the like.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Inventors: Maxwell Christopher RENKE, Benjamin M. SCHULTZ, Yevgeniy BAK, Vijaykumar SHARMA, Apurva Ashvinkumar THANKY, Hari R. PULAPAKA
  • Patent number: 11157306
    Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: October 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Arun U. Kishan
  • Publication number: 20210149816
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 20, 2021
    Inventors: Yevgeniy BAK, Mehmet IYIGUN, Jonathan E. LANGE
  • Patent number: 10929167
    Abstract: Communicating a low-latency event across a virtual machine boundary. Based on an event signaling request by a first process running at a first virtual machine, the first virtual machine updates a shared register that is accessible by a second virtual machine. Updating the shared register includes updating a signal stored in the shared register. The first virtual machine sends an event signal message, which includes a register identifier, through a virtualization fabric to the second virtual machine. The second virtual machine receives the event signaling message and identifies the register identifier from the message. Based on the register identifier, the second virtual machine reads the shared register, identifying a value of the signal stored in the shared register. Based at least on the value of the signal comprising a first value, the second virtual machine signals a second process running at the second virtual machine.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: February 23, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jason Lin, Gregory John Colombo, Mehmet Iyigun, Yevgeniy Bak, Christopher Peter Kleynhans, Stephen Louis-Essman Hufnagel, Michael Ebersol, Ahmed Saruhan Karademir, Shawn Michael Denbow, Kevin Broas, Wen Jia Liu
  • Patent number: 10901911
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: January 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Jonathan E. Lange
  • Publication number: 20200394065
    Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.
    Type: Application
    Filed: August 30, 2020
    Publication date: December 17, 2020
    Inventors: Yevgeniy BAK, Mehmet IYIGUN, Arun U. KISHAN
  • Patent number: 10761876
    Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Arun U. Kishan