Patents by Inventor Yew Fatt (Edwin) Kok

Yew Fatt (Edwin) Kok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for varying phase shifts in periodic signals
    Patent number: 8120407
    Abstract: A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: February 21, 2012
    Assignee: Altera Corporation
    Inventors: Teng Chow Ooi, Eng Huat Lee, Chuan Khye Chai, Yew Fatt (Edwin) Kok, Sergey Shumarayev
  • CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
    Publication number: 20080258772
    Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
    Type: Application
    Filed: June 26, 2008
    Publication date: October 23, 2008
    Applicant: ALTERA CORPORATION
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt (Edwin) Kok, Kar Keng Chua
  • Clock signal networks for structured ASIC devices
    Patent number: 7404169
    Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: July 22, 2008
    Assignee: Altera Corporation
    Inventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt (Edwin) Kok, Kar Keng Chua