Patents by Inventor Yew Fatt Kok
Yew Fatt Kok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230096585Abstract: The present disclosure is directed to improving compatibility between chiplets integrated with disparate chiplet interfaces. To reduce compatibility issues due non-matching bump maps, a dual-mode bump map assignment may be implemented to enable a chiplet to utilize multiple signal number sequence assignments. Additionally, a modularized Advanced Interface Bus (AIB) interface may be implemented to reduce channel mismatch in AIB -UCIe multi-channel interoperability.Type: ApplicationFiled: December 5, 2022Publication date: March 30, 2023Inventors: Yanjing Ke, Yew Fatt Kok
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Publication number: 20220390694Abstract: The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.Type: ApplicationFiled: June 4, 2021Publication date: December 8, 2022Applicant: Intel CorporationInventors: Chia-Pin Chiu, Kaveh Hosseini, Thu Ngoc Tran, Yew Fatt Kok, Kumar Abhishek Singh, Xiaoqian Li, Marely Tejeda Ferrari, Ravindranath Mahajan, Kevin Ma, Casey Thielen
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Patent number: 10495686Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.Type: GrantFiled: August 22, 2017Date of Patent: December 3, 2019Assignee: Altera CorporationInventors: Wai Tat Wong, Edwin Yew Fatt Kok, Wilfred Wee Kee King, Tee Wee Tan
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Publication number: 20170350937Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Wai Tat Wong, Edwin Yew Fatt Kok, Wilfred Wee Kee King, Tee Wee Tan
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Patent number: 9778312Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.Type: GrantFiled: October 16, 2013Date of Patent: October 3, 2017Assignee: Altera CorporationInventors: Wai Tat Wong, Edwin Yew Fatt Kok, Wilfred Wee Kee King, Tee Wee Tan
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Patent number: 9225335Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.Type: GrantFiled: November 19, 2013Date of Patent: December 29, 2015Assignee: ALTERA CORPORATIONInventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
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Publication number: 20140077839Abstract: Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: ALTERA CORPORATIONInventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
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Patent number: 8595658Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.Type: GrantFiled: June 26, 2008Date of Patent: November 26, 2013Assignee: Altera CorporationInventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
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Patent number: 8397096Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.Type: GrantFiled: May 21, 2010Date of Patent: March 12, 2013Assignee: Altera CorporationInventors: Sergey Shumarayev, Edwin Yew Fatt Kok, Lip Kai Soh, Chee Hong Aw, Tee Wee Tan
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Patent number: 8261141Abstract: Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.Type: GrantFiled: January 11, 2011Date of Patent: September 4, 2012Assignee: Altera CorporationInventors: Kok Heng Choe, Edwin Yew Fatt Kok, Kar Keng Chua
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Patent number: 8253448Abstract: A circuit includes first and second frequency divider circuits and first storage circuits. Each of the first and the second frequency divider circuits receives periodic input signals and generates a periodic output signal having a frequency of one of the periodic input signals in a bypass mode. The periodic output signal of each of the first and the second frequency divider circuits has a fraction of a frequency of one of the periodic input signals in a frequency divider mode. Each of the first storage circuits stores an enable signal in response to the periodic output signal of one of the first frequency divider circuits. The enable signals stored in the first storage circuits enable the second frequency divider circuits in the frequency divider mode. The circuit may include second storage circuits storing enable signals that enable a subset of the first frequency divider circuits in the frequency divider mode.Type: GrantFiled: July 19, 2010Date of Patent: August 28, 2012Assignee: Altera CorporationInventors: Chuan Thim Khor, Chuan Khye Chai, Edwin Yew Fatt Kok
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Publication number: 20110285434Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.Type: ApplicationFiled: May 21, 2010Publication date: November 24, 2011Inventors: Sergey Shumarayev, Edwin Yew Fatt Kok, Lip Kai Soh, Chee Hong Aw, Tee Wee Tan
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Patent number: 7882408Abstract: Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically and automatically, to provide accurate and high performance memory operations. For example, timing settings for the control signals can be determined such that data written/read from the memory are accurate. The timing setting can also be changed to provide faster memory operations while still providing accuracy. A feedback system using a control block and a dummy mimicking concept are also provided.Type: GrantFiled: October 11, 2006Date of Patent: February 1, 2011Assignee: Altera CorporationInventors: Kok Heng Choe, Edwin Yew Fatt Kok, Kar Keng Chua
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Patent number: 7679397Abstract: Techniques are provided for controlling an on-chip termination (OCT) in an output driver. The OCT control circuit calibrates the effective resistance of transistors in the output driver to match an external resistor using a feedback loop. The feedback loop monitors the output voltage and generates an analog calibration signal that varies the output impedance of a selected group of the output transistors that are enabled to drive the output terminal. Digital signals under the control of the user select the number of output transistors to be enabled based on the output driver requirements of the circuit. The analog calibration signal varies the signal level driving the selected output transistors to modify the effective output impedance of the circuit for better termination matching.Type: GrantFiled: August 5, 2005Date of Patent: March 16, 2010Assignee: Altera CorporationInventors: Yew Fatt Kok, Chooi Pei Lim, Kok Heng Choe
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Patent number: 7164289Abstract: Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.Type: GrantFiled: January 21, 2005Date of Patent: January 16, 2007Assignee: Altera CorporationInventors: Kok Heng Choe, Edwin Yew Fatt Kok, Kar Keng Chua
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Patent number: 7071731Abstract: Memory performance of an integrated circuit, such as a programmable logic integrated circuit, is increased by pipelining. In a single clock cycle, more than one operation may be performed on the memory, which improves bandwidth. In an implementation, the memory architecture having one port supports pipelining, so reading from and writing to the memory can be accomplished in a one clock cycle and both Read and Write operation can occupy the full clock cycle at the same time on the same port. The pipelining architecture has relatively minimal circuit changes compared to a standard memory architecture which not supporting simultaneous-clock-cycle reads and writes, without requiring two or more ports.Type: GrantFiled: January 21, 2005Date of Patent: July 4, 2006Assignee: Altera CorporationInventors: Kok Heng Choe, Edwin Yew Fatt Kok, Kar Keng Chua
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Patent number: 7046566Abstract: Circuitry and methods are provided for controlling memory operation by comparing bit line voltages to preset reference voltages. By relying on bit line voltage levels to determine when to start and end each stage of a read or write operation, reliance on precisely tuned delay chains is removed. Parasitic effects are automatically accounted for, as well as process, voltage, and temperature variations. This precise matching of operation timing to memory bit line conditions results in improved system performance.Type: GrantFiled: December 6, 2004Date of Patent: May 16, 2006Assignee: Altera CorporationInventors: Kok Heng Choe, Edwin Yew Fatt Kok, Kar Keng Chua