Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

Abstract: Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.

Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

Abstract: Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.

Abstract: Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.

Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.