Abstract: A delay control circuit includes a first delay unit, a signal regulation unit, a selector and a second delay unit. The first delay unit is used for delaying an input signal and generates a delayed input signal. The signal regulation unit is coupled to the first delay unit and outputs a rising edge delay signal and a falling edge delay signal according to the input signal and the delayed input signal. The selector is coupled with the signal regulation unit and outputs one of rising edge delay signal and falling edge delay signal according to the control signal. The second delay unit is coupled to the selector for delaying the output of the selector and outputting an output signal.

Abstract: A delay control circuit includes a first delay unit, a signal regulation unit, a selector and a second delay unit. The first delay unit is used for delaying an input signal and generates a delayed input signal. The signal regulation unit is coupled to the first delay unit and outputs a rising edge delay signal and a falling edge delay signal according to the input signal and the delayed input signal. The selector is coupled with the signal regulation unit and outputs one of rising edge delay signal and falling edge delay signal according to the control signal. The second delay unit is coupled to the selector for delaying the output of the selector and outputting an output signal.

Abstract: A timing-flexible flip-flop element with at least one extra delayed output signal. The timing-flexible flip-flop element includes a flip-flop logic circuit for generating a standard output signal and a delay cell for receiving the standard output signal to generate a delayed output signal. Because the timing-flexible flip-flop element of the invention has at least one extra delayed output signal, the delayed output signal for the flip-flop may be selected for the path that needs longer hold time. Therefore, it is unnecessary to insert any delay cell to the path with insufficient hold time. The timing-flexible flip-flop element can be implemented in the cell-based synthesis design flow.