Patents by Inventor Yew Tuck Chow
Yew Tuck Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9548378Abstract: A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.Type: GrantFiled: February 9, 2012Date of Patent: January 17, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Stephan Kronholz, Nadja Zakowsky, Yew Tuck Chow
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Patent number: 9018065Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.Type: GrantFiled: May 8, 2012Date of Patent: April 28, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Joanna Wasyluk, Yew Tuck Chow, Stephan Kronholz, Lindarti Purwaningsih, Ines Becker
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Patent number: 8658543Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.Type: GrantFiled: February 7, 2012Date of Patent: February 25, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Joanna Wasyluk, Stephan Kronholz, Yew-Tuck Chow, Richard J. Carter, Berthold Reimer, Kai Tern Sih
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Publication number: 20130302973Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.Type: ApplicationFiled: May 8, 2012Publication date: November 14, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Joanna Wasyluk, Yew Tuck Chow, Stephan Kronholz, Lindarti Purwaningsih, Ines Becker
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Publication number: 20130299874Abstract: CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Joanna Wasyluk, Berthold Reimer, Carsten Reichel, Jamie Schaeffer, Yew Tuck Chow, Stephan Kronholz, Andreas Ott
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Publication number: 20130210216Abstract: A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stephan Kronholz, Nadja Zakowsky, Yew Tuck Chow
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Publication number: 20130203244Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Joanna Wasyluk, Stephan Kronholz, Yew-Tuck Chow, Richard J. Carter, Berthold Reimer, Kai Tern Sih
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Patent number: 8143651Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: GrantFiled: August 2, 2010Date of Patent: March 27, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
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Publication number: 20100301424Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: ApplicationFiled: August 2, 2010Publication date: December 2, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
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Patent number: 7767577Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: GrantFiled: February 14, 2008Date of Patent: August 3, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
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Publication number: 20090206408Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG