Patents by Inventor Yezhou FANG
Yezhou FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210357081Abstract: The present disclosure provides a touch display panel. Specifically, the touch display panel includes a display area and a non-display area located in a periphery of the display area. In addition, the touch display panel further includes a touch circuit and a peripheral circuit, the peripheral circuit is located in the non-display area; and a conductive pattern. The conductive pattern is adapted to cooperate with at least a portion of the peripheral circuit to form a capacitance, and is further electrically insulated from the touch circuit and the peripheral circuit.Type: ApplicationFiled: May 30, 2018Publication date: November 18, 2021Inventors: Yanyan ZHAO, Jingyi XU, Fuqiang TANG, Yezhou FANG, Yuelin WANG, Yanan YU, Xu ZHANG
-
Patent number: 11177425Abstract: The present disclosure provides a driving backplane, a method for manufacturing the same, and a display device. The driving backplane includes: a substrate; and a bonding layer located on a side of the substrate and configured to bond with a plurality of Micro LEDs arranged in an array, wherein the bonding layer comprises a bonding metal layer and a conductive protection layer that are stacked sequentially along a direction away from the substrate, an orthographic projection of the conductive protection layer on the substrate substantially coinciding with an orthographic projection of the bonding metal layer on the substrate.Type: GrantFiled: March 23, 2020Date of Patent: November 16, 2021Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Feng Li, Yezhou Fang
-
Patent number: 11163204Abstract: An array substrate, a display panel including the same, and a display device are provided. The array substrate includes: a base substrate and a planarization layer on the base substrate. A first conductive layer is disposed on a side of the planarization layer away from the base substrate. A first passivation layer is disposed on a side of the first conductive layer and the side of the planarization layer not being covered by the first conductive layer, away from the base substrate, and provided with a plurality of stress release openings. An insulating layer is disposed in the stress release openings and on a side of the first passivation layer away from the planarization layer. A second conductive layer is disposed on a side of the insulating layer away from the planarization layer.Type: GrantFiled: March 6, 2020Date of Patent: November 2, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Kai Li, Bo Ma
-
Publication number: 20210325719Abstract: The present disclosure is related to a display panel. The display panel may include a first light shielding layer (101) in a display region and a second light shielding layer (212) opposite the first light shielding layer (101) in the display region. The first light shielding layer (101) may include a plurality of first openings (112), and the second light shielding layer (212) may include a plurality of second openings (222). The display region may include a middle display region (20A) and a periphery display region (20B). An area of each of the plurality of the first openings (112) in the periphery display region (20B) may be smaller than an area of each of the plurality of the first openings (112) in the middle display region (20A).Type: ApplicationFiled: July 19, 2018Publication date: October 21, 2021Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE Technology Group Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Xiaokang Wang, Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Le Sun, Wei Zhang, Xin Zhao, Zhijun Niu, Yezhou Fang, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
-
Patent number: 11127885Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.Type: GrantFiled: March 22, 2020Date of Patent: September 21, 2021Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
-
Patent number: 11121226Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.Type: GrantFiled: January 29, 2019Date of Patent: September 14, 2021Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Lei Yan, Feng Li, Yezhou Fang, Jun Fan, Lei Li, Yanyan Meng, Lei Yao, Jinjin Xue, Chenglong Wang, Jinfeng Wang, Lin Hou, Zhixuan Guo
-
Publication number: 20210249450Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Inventors: Jinjin Xue, Dawei Shi, Feng Li, Lei Yao, Wentao Wang, Haifeng Xu, Lu Yang, Lin Hou, Jinfeng Wang, Mei Li, Yezhou Fang
-
Publication number: 20210217894Abstract: A CMOS thin film transistor, a method for manufacturing the same, and an array substrate are provided. The method includes: forming a semiconductor layer including an N-type region and a P-type region on a substrate, the N-type region is divided into a first region, a second region, a third region, a fourth region and a fifth region, the P-type region is divided into a sixth region, a seventh region and an eighth region; performing first N-type ion doping on the first region and the fifth region; performing first P-type ion doping on the N-type region; performing second P-type ion doping on the N-type region and the P-type region; performing second N-type ion doping on the first region, the second region, the fourth region, the fifth region, the sixth region and the eighth region; and performing third P-type ion doping on the sixth region and the eighth region.Type: ApplicationFiled: December 25, 2019Publication date: July 15, 2021Inventors: Lei YAO, Yezhou FANG, Feng LI, Lei YAN, Jinjin XUE, Chenglong WANG, Yanyan MENG, Jinfeng WANG, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI
-
Publication number: 20210209789Abstract: The present disclosure relates to an apparatus and method for detecting display panel defects and a microscope. The apparatus for detecting display panel defects comprises: a switch component connected to a microscope; a detection component, which is disposed on the switch component and has a first visual area, the detection component being configured to detect a position of a microscopic defect in a display panel; and a marking component, which is disposed on the switch component and has a second visual area with a smaller area than the first visual area, the marking component being configured to mark the position of the microscopic defect in the display panel, wherein the switch component is configured to rotate the marking component to a position of the detection component and mark a position of the microscopic defect by the marking component after the detection component detects the position.Type: ApplicationFiled: December 11, 2017Publication date: July 8, 2021Applicants: BOE TechnologyGroup Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.Inventors: Tienan LIU, Yuelin WANG, Yanming WANG, Weixin MENG, Yezhou FANG, Jingyi XU, Yanyan ZHAO, Yanwei REN
-
Patent number: 11031419Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.Type: GrantFiled: April 12, 2019Date of Patent: June 8, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jinjin Xue, Dawei Shi, Feng Li, Lei Yao, Wentao Wang, Haifeng Xu, Lu Yang, Lin Hou, Jinfeng Wang, Mei Li, Yezhou Fang
-
Publication number: 20210159364Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.Type: ApplicationFiled: March 22, 2020Publication date: May 27, 2021Inventors: Hong LIU, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
-
Publication number: 20210157185Abstract: An array substrate, a display panel including the same, and a display device are provided. The array substrate includes: a base substrate and a planarization layer on the base substrate. A first conductive layer is disposed on a side of the planarization layer away from the base substrate. A first passivation layer is disposed on a side of the first conductive layer and the side of the planarization layer not being covered by the first conductive layer, away from the base substrate, and provided with a plurality of stress release openings. An insulating layer is disposed in the stress release openings and on a side of the first passivation layer away from the planarization layer. A second conductive layer is disposed on a side of the insulating layer away from the planarization layer.Type: ApplicationFiled: March 6, 2020Publication date: May 27, 2021Inventors: Hong LIU, Yezhou FANG, Fengguo WANG, Xinguo WU, Zhixuan GUO, Haidong WANG, Liang TIAN, Kai LI, Bo MA
-
Patent number: 11004381Abstract: The present disclosure provides an array substrate and a display device for reducing the space occupied by the antenna inside the mobile phone, so as to reduce the thickness of the mobile phone and make the mobile phone thinner and lighter. The array substrate according to the present disclosure includes dummy signal lines and a conductive portion. The dummy signal lines and the conductive portion are disposed in different layers. An insulating layer is disposed between the dummy signal lines and the conductive portion. A via is disposed on the insulating layer. The dummy signal line is connected to the conductive portion through the via. The dummy signal line and the conductive portion are used to form an antenna.Type: GrantFiled: September 20, 2018Date of Patent: May 11, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yanwei Ren, Yezhou Fang, Jingyi Xu, Xin Zhao, Min Liu, Chaochao Sun
-
Patent number: 10977970Abstract: The disclosure provides an array substrate, a display device, a detecting apparatus and a detecting method for detecting a defect connection of a data line. A data signal input bus of the array substrate of the present disclosure applies a data signal to each pixel unit, and a detection line is added on one side of the array substrate opposite to the data signal input bus, when the product is detected, the data signal input bus inputs the normal data signal, the detection line on the other side inputs a signal having a polarity contrary to that of the data signal. At a position of the data line existing defect connection, heat is generated and the data line is burnt at the position existing defect connection.Type: GrantFiled: October 25, 2018Date of Patent: April 13, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Wei Zhang, Yezhou Fang, Le Sun, Wenlong Zhang, Guangshuai Wang
-
Publication number: 20210089154Abstract: Embodiments of the present disclosure provide an array substrate, a method of manufacturing the array substrate, a display panel and a display apparatus. The array substrate includes: a substrate; a touch pad disposed on a side of the substrate; a first planarization layer disposed on a side of the touch pad facing away from the substrate; a first passivation layer disposed on a side of the first planarization layer facing away from the touch pad; a touch electrode layer disposed on a side of the first passivation layer facing away from the first planarization layer; and a first via hole sequentially passing through at least the first planarization layer and the first passivation layer. The touch electrode layer is electrically connected to the touch pad through the first via hole.Type: ApplicationFiled: March 19, 2020Publication date: March 25, 2021Inventors: Chenglong Wang, Yezhou Fang, Feng Li, Xinguo Wu, Xiaogang Zhu, Guojiang Yu
-
Publication number: 20210050497Abstract: The present disclosure provides a driving backplane, a method for manufacturing the same, and a display device. The driving backplane includes: a substrate; and a bonding layer located on a side of the substrate and configured to bond with a plurality of Micro LEDs arranged in an array, wherein the bonding layer comprises a bonding metal layer and a conductive protection layer that are stacked sequentially along a direction away from the substrate, an orthographic projection of the conductive protection layer on the substrate substantially coinciding with an orthographic projection of the bonding metal layer on the substrate.Type: ApplicationFiled: March 23, 2020Publication date: February 18, 2021Inventors: Feng Li, Yezhou Fang
-
Patent number: 10921661Abstract: Embodiments of the present disclosure provide a color filter substrate and a method of manufacturing the same, and a display panel. The color filter substrate includes a base substrate and a light shielding pattern on the base substrate. The light shielding pattern is provided with a groove, which divides the light shielding pattern into an outer light shielding sub-pattern corresponding to a peripheral region of the color filter substrate and an inner light shielding sub-pattern arranged at a position corresponding to a display area of the color filter substrate; an electrically conductive pattern is provided in at least part of a region in the groove and electrically connected with the inner light shielding sub-pattern and/or the outer light shielding sub-pattern.Type: GrantFiled: October 20, 2017Date of Patent: February 16, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Peirong Huo, Yezhou Fang, Shicheng Sun, Jingyi Xu
-
Patent number: 10903249Abstract: An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.Type: GrantFiled: March 29, 2018Date of Patent: January 26, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Wei Zhang, Hui Li, Tianlei Shi, Jonguk Kwak, Yezhou Fang, Wenlong Zhang, Xu Zhang, Zhijun Niu, Ruize Jiang, Yanwei Ren, Yu Liu
-
Publication number: 20210020755Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.Type: ApplicationFiled: January 29, 2019Publication date: January 21, 2021Inventors: Lei YAN, Feng LI, Yezhou FANG, Jun FAN, Lei LI, Yanyan MENG, Lei YAO, Jinjin XUE, Chenglong WANG, Jinfeng WANG, Lin HOU, Zhixuan GUO
-
Publication number: 20210020787Abstract: Provided is a transistor, the transistor being located on a base and having an active layer, and the active layer of the transistor comprising a plurality of semiconductor patterns which are stacked, wherein the plurality of semiconductor patterns are electrically connected; and orthographic projections of any two of the semiconductor patterns on the base are different in shape. A method of manufacturing a transistor, a transistor device, and a display substrate and apparatus are also provided.Type: ApplicationFiled: June 29, 2020Publication date: January 21, 2021Inventors: Lei Yan, Jianyun Xie, Yezhou Fang, Jun Fan, Feng Li