Patents by Inventor Yi-An Lai

Yi-An Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11764760
    Abstract: Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
  • Publication number: 20230267086
    Abstract: A serial peripheral interface circuit includes a serial peripheral interface device with a master-in-slave-out (MISO) line, a master-out-slave-in (MOSI) line, a serial clock (SCLK) line and a slave select (SS) line, a first conducting line, a second conducting line, a first resistor connecting the MISO line and the first conducting line, and a second resistor connecting the MOSI line and the second conducting line.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Inventors: Hung-Yi LAI, Cheng-Hung HO, Hsin-Wen LIN
  • Patent number: 11719977
    Abstract: A light reflecting structure, a backlight module, and a display device are provided. The light reflecting structure is configured to reflect light emitted from plural light emitting units. The light reflecting structure includes a bottom portion and plural sidewall portions. The sidewall portions are erected on the bottom portion. The sidewall portions respectively and correspondingly surround the light-emitting units, and the light emitted from each of the light-emitting units can be directed to a light reflecting surface corresponding to each of the sidewall portions to be reflected outward. A distance P is defined between any two adjacent sidewall portions, and each of the sidewall portions has a height H1. The distance P and the height H1 satisfy a first inequality, and the first inequality is H1<P/2×tan ?. ? represents a complementary angle of a half light-intensity angle of each of the light-emitting units.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: August 8, 2023
    Assignees: Radiant(Guangzhou) Opto-Electronics Co., Ltd, Radiant Opto-Electronics Corporation
    Inventors: Hui-Yu Huang, Hsiu-Yi Lai, Shih-Cheng Hsiao, Shu-An Tsai, Pei-Ling Kao, I-Cheng Liu
  • Publication number: 20230236738
    Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 27, 2023
    Inventors: CHUNG-TING HUANG, CHUNG-YI LAI, TING-CHIANG LIU
  • Publication number: 20230204655
    Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.
    Type: Application
    Filed: May 5, 2022
    Publication date: June 29, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
  • Publication number: 20230176341
    Abstract: Wide angle lens for imaging objects disposed away from the optical axis towards the periphery of the field of view.
    Type: Application
    Filed: August 5, 2022
    Publication date: June 8, 2023
    Inventors: Maksim MAKEEV, Mark S. SCHNITTMAN, Xiaoyu MIAO, Ming-lin LEE, Cheng-Yi LAI, Chien-Hung CHOU
  • Publication number: 20230154912
    Abstract: A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 18, 2023
    Inventors: Chan-Hong Chern, Yi-An Lai
  • Patent number: 11623674
    Abstract: A rail vehicle system, a rail vehicle, and a visual sensing device are provided. The rail vehicle system includes a system control device, a rail, and a rail vehicle. The rail vehicle includes a processing device and the visual sensing device. In a process where the rail vehicle travels along the rail, the visual sensing device captures images in front of the rail vehicle, and the visual sensing device emits a laser beam toward a front side of the rail vehicle. The visual sensing device receives the reflected laser beam to generate a laser sensing data. The processing device determines whether or not to change at least one of a travel direction and a travel speed of the rail vehicle according to the images captured by the visual sensing device and the laser sensing data.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 11, 2023
    Assignee: MIRLE AUTOMATION CORPORATION
    Inventors: Ming-Hsiu Hsu, Hsing-Lu Huang, Long-Yi Lai
  • Publication number: 20230091208
    Abstract: An optical imaging lens assembly, which is applied for an endoscopic optical device, from an object side to an image side aligned in order includes a first lens element, a second lens element and a third lens element. The first lens element has negative refracting power, and further has a first convex object-side surface and a first image-side surface. The second lens element has positive refracting power, and further has a second convex object-side surface and a second concave image-side surface. The third lens element has positive refracting power, and further has a third convex image-side surface and a third object-side surface.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Applicant: ALTEK BIOTECHNOLOGY CORPORATION
    Inventors: Cheng-Yi Lai, Yang-Chang Chien
  • Publication number: 20230076967
    Abstract: An automatic optimization method and an automatic optimization system of a diagnosis model are provided. The automatic optimization method includes: obtaining equipment parameters; selecting a target model; selecting and converting a hyperparameter into a gene sequence, randomly generating a plurality of gene sequences to be optimized and adding them to a gene sequence set; performing a gene evolution process to generate a plurality of progeny gene sequences; performing a region search process on the plurality of progeny gene sequences to generate a plurality of new progeny gene sequences and add them to the gene sequence set; and in response to meeting the evolution completion condition, using the gene sequence set as an optimal gene sequence set for configuration of the target model and generation of a plurality of candidate diagnosis models.
    Type: Application
    Filed: October 21, 2021
    Publication date: March 9, 2023
    Inventors: CI-YI LAI, CHENG-HUI CHEN, HSAIO-YU WANG, HUAI-CHE HONG
  • Publication number: 20220415720
    Abstract: A method of fabricating a device involves forming a plurality of structures, such that each structure of the plurality includes a substrate and an epitaxial layer on the substrate. The epitaxial layer and the substrate have a lattice mismatch. The method further includes forming an electrical contact on the epitaxial layer of a selected structure of the plurality of structures and performing a current leakage measurement quality control test for the selected structure of the plurality of structures through the electrical contact. The method also involves forming a device on each of the remaining structures of the plurality of structures if the selected structure passed the leakage measurement quality control test or discarding each of the remaining structures of the plurality of structures if the selected structure did not pass the leakage measurement quality control test.
    Type: Application
    Filed: February 22, 2022
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chih-Hua Wang, Chan-Hong Chern, Cheng-Hsiang Hsieh
  • Publication number: 20220348972
    Abstract: Mutant thioesterases having enhanced medium chain substrate activity, polynucleotides encoding and configured to express the mutant thioesterases in a transformed host cell, host cells transformed to contain the polynucleotides, and methods of using same.
    Type: Application
    Filed: July 5, 2022
    Publication date: November 3, 2022
    Applicant: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Brian F Pfleger, Nestor Hemandez-Lozada, Rung-Yi Lai
  • Publication number: 20220336295
    Abstract: A manufacturing method of group III-V semiconductor package is provided. The manufacturing method includes the following steps. A wafer comprising group III-V semiconductor dies therein is provided. A chip probing (CP) process is performed to the wafer to determine reliabilities of the group III-V semiconductor dies, wherein the CP process comprises performing a multi-step breakdown voltage testing process to the group III-V semiconductor dies to obtain a first portion of dies of the group III-V semiconductor dies with breakdown voltages to be smaller than a predetermined breakdown voltage. A singulation process is performed to separate the group III-V semiconductor dies from the wafer. A package process is performed to form group III-V semiconductor packages including the group III-V semiconductor dies. A final testing process is performed on the group III-V semiconductor packages.
    Type: Application
    Filed: September 15, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chan-Hong Chern, Chih-Hua Wang, Chu-Fu Chen, Kun-Lung Chen
  • Patent number: 11442255
    Abstract: Wide angle lens for imaging objects disposed away from the optical axis towards the periphery of the field of view.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 13, 2022
    Assignee: Owl Labs, Inc.
    Inventors: Maksim Makeev, Mark S Schnittman, Xiaoyu Miao, Ming-lin Lee, Cheng-Yi Lai, Chien-Hung Chou
  • Publication number: 20220257973
    Abstract: The present invention provides a method for manufacturing a neural probe incorporated with an optical waveguide. The method for manufacturing a neural probe incorporated with an optical waveguide comprises the following steps. A mold-filling step, for providing a base with at least one groove formed therein. A disposing step, for disposing and overlaying a substrate having a plurality of electrode parts on the groove of the base. A combining step, for solidifying the photosensitive adhesive by a solidification process, the solidified photosensitive adhesive forming an optical waveguide and being combined with the substrate. A mold-releasing step, for removing the base from the optical waveguide and the substrate, the substrate and the optical waveguide forming a product.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Inventors: Hsin-Yi Lai, You-Yin Chen
  • Patent number: 11408014
    Abstract: Mutant thioesterases having enhanced medium chain substrate activity, polynucleotides encoding and configured to express the mutant thioesterases in a transformed host cell, host cells transformed to contain the polynucleotides, and methods of using same.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: August 9, 2022
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Brian F. Pfleger, Nestor Hernandez-Lozada, Rung-Yi Lai
  • Publication number: 20220175964
    Abstract: Synthetic nucleic acids encoding mini and microdystrophin genes comprising the membrane binding motifs or domains of the R10-R11-R12 region are provided. Also provided are vectors, host cells, and related methods of using the same to treat a subject suffering from Duchenne muscular dystrophy (DMD), Becker muscular dystrophy (BMD) or X-linked dilated cardiomyopathy (XLDC), or for ameliorating one or more adverse effects of DMD, BMD, or XLDC. Also provided are a fusion protein comprising a nNOS binding domain of dystrophin R16-R17 that is operably linked to a syntrophin PDZ domain and synthetic nucleic acids comprising the same that can be used to treat subjects with diseases characterized by loss of sarcolemmal neuronal nitric oxide synthase (nNOS) activity.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 9, 2022
    Inventors: Dongsheng Duan, Yi Lai, Junling Zhao, Yongping Yue
  • Patent number: 11351394
    Abstract: The present invention provides a method for manufacturing a neural probe incorporated with an optical waveguide. The method for manufacturing a neural probe incorporated with an optical waveguide comprises the following steps. A mold-filling step, for providing a base with at least one groove formed therein. A disposing step, for disposing and overlaying a substrate having a plurality of electrode parts on the groove of the base. A combining step, for solidifying the photosensitive adhesive by a solidification process, the solidified photosensitive adhesive forming an optical waveguide and being combined with the substrate. A mold-releasing step, for removing the base from the optical waveguide and the substrate, the substrate and the optical waveguide forming a product.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 7, 2022
    Inventors: Hsin-Yi Lai, You-Yin Chen
  • Patent number: 11334131
    Abstract: In example implementations, an apparatus is provided. The apparatus includes a plurality of power inputs, a plurality of power outputs, a power management component, and a power source capability information translation component. The plurality of power inputs is coupled to power sources. The plurality of power outputs is coupled to electronic devices. The power management component is coupled to the plurality of power inputs and the plurality of power outputs to manage deliver of power. The power source capability information translation component is coupled to the power management component and an external source that provides a power source capability information of a power source connected to a power input of the plurality of power inputs. The power management component delivers the power from the power source to a power output of the plurality of power outputs in accordance with the power source capability information received from the external source.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 17, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Seiler, Adolfo Gomez, Chun-Yi Lai, Hoang Van Ngo
  • Publication number: 20220137459
    Abstract: A light reflecting structure, a backlight module, and a display device are provided. The light reflecting structure is configured to reflect light emitted from plural light emitting units. The light reflecting structure includes a bottom portion and plural sidewall portions. The sidewall portions are erected on the bottom portion. The sidewall portions respectively and correspondingly surround the light-emitting units, and the light emitted from each of the light-emitting units can be directed to a light reflecting surface corresponding to each of the sidewall portions to be reflected outward. A distance P is defined between any two adjacent sidewall portions, and each of the sidewall portions has a height H1. The distance P and the height H1 satisfy a first inequality, and the first inequality is H1<P/2×tan ?. ? represents a complementary angle of a half light-intensity angle of each of the light-emitting units.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Inventors: Hui-Yu HUANG, Hsiu-Yi LAI, Shih-Cheng HSIAO, Shu-An TSAI, Pei-Ling KAO, I-Cheng LIU