Abstract: This disclosure relates to rechargeable battery packs and or rechargeable battery modules consisting of electrochemical cells in general and more specifically to lithium metal anode secondary electrochemical cells and the supporting mechanical structure of such packs or modules which apply and maintain a high and uniform normal compression pressure to the face of the interconnected cells of said battery packs, modules or individual cells, in order to suppress dendrite formation during charge and maintain a low cell impedance during charge and discharge. This is achieved with the use of a compression assembly having a compressible sheet with desired properties.

Abstract: An apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Abstract: A display device includes a substrate, gate lines, data lines, gate tracking lines, and dummy gate tracking lines. The gate lines and the data lines are arranged perpendicularly. Each gate tracking line is disposed between one parts of two adjacent data lines, and substantially parallel to the data lines. Each dummy gate tracking line is electrically disconnected to the gate lines, disposed between other parts of two adjacent data lines, and substantially parallel to the data lines.

Abstract: An exemplary display device includes multiple pixels, first through third gate lines and a data line. The pixels include first through third pixels. The first through third gate lines respectively are electrically coupled with the first through third pixels and for deciding whether to enable the first through third pixels. The first pixel is electrically coupled to the data line to receive a display data provided by the data line. The second pixel is electrically coupled to the first pixel to receive a display data provided by the data line through the first pixel. The third pixel is electrically coupled to the second pixel to receive a display data provided by the data line through both the first pixel and the second pixel. A display driving method adapted to be implemented in the display device also is provided.

Abstract: An exemplary display device includes multiple pixels, first through third gate lines and a data line. The pixels include first through third pixels. The first through third gate lines respectively are electrically coupled with the first through third pixels and for deciding whether to enable the first through third pixels. The first pixel is electrically coupled to the data line to receive a display data provided by the data line. The second pixel is electrically coupled to the first pixel to receive a display data provided by the data line through the first pixel. The third pixel is electrically coupled to the second pixel to receive a display data provided by the data line through both the first pixel and the second pixel. A display driving method adapted to be implemented in the display device also is provided.

Abstract: A display device includes a substrate, gate lines, data lines, gate tracking lines, and dummy gate tracking lines. The gate lines and the data lines are arranged perpendicularly. Each gate tracking line is disposed between one parts of two adjacent data lines, and substantially parallel to the data lines. Each dummy gate tracking line is electrically disconnected to the gate lines, disposed between other parts of two adjacent data lines, and substantially parallel to the data lines.

Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Abstract: A substrate having a switching device and a storage capacitor thereon is provided. A protective layer is formed on the substrate. A patterned organic material layer is formed on the protective layer, wherein bump patterns are formed on a part of the patterned organic material layer and the patterned organic material layer has first openings to expose the partial protective layer. A reflective layer is formed on the patterned organic material layer and the exposed protective layer. A first patterned photoresist layer is formed on a part of the reflective layer, wherein the first patterned photoresist layer has second openings to expose a part of the reflective layer. The first patterned photoresist layer is used as an etching mask to form a first contact hole and a second contact hole. The first patterned photoresist layer is removed. A pixel electrode is formed on the patterned organic material layer.

Abstract: A pixel structure includes a substrate, a floating light-shielding pattern disposed on the substrate, an insulating layer disposed on the substrate and the light-shielding pattern, a data line disposed over and corresponding to the light-shielding pattern, a dielectric layer disposed on the data line and the insulating layer, and a third layer conductive pattern disposed on the dielectric layer. The third layer conductive pattern includes a common line and a common pattern. The common pattern includes two common branches arranged in parallel, and there is a space between the two common branches and over the data line.

Abstract: A pixel structure includes a substrate, a floating light-shielding pattern disposed on the substrate, an insulating layer disposed on the substrate and the light-shielding pattern, a data line disposed over and corresponding to the light-shielding pattern, a dielectric layer disposed on the data line and the insulating layer, and a third layer conductive pattern disposed on the dielectric layer. The third layer conductive pattern includes a common line and a common pattern. The common pattern includes two common branches arranged in parallel, and there is a space between the two common branches and over the data line.

Abstract: The present invention discloses a membrane zeta potential measuring system which comprises a first measuring course and a second measuring course. The provided system calculates the zeta potential of the membrane pores based on a first potential drop measured from the first measuring course, and calculates the zeta potential of the membrane surface based on a second potential drop measured from the second measuring course.

Abstract: A sealant region pattern for a liquid crystal display apparatus and a method for fabricating the same. The method comprises providing a first substrate and a second substrate opposite thereto, forming a predetermined material layer on the first substrate, forming an organic material pattern layer having openings of a saw tooth pattern on the predetermined material layer to expose the surface of the predetermined material layer underneath, The surface of the predetermined material layer and the sidewall of the organic material pattern layer form a predetermined angle.

Abstract: A sealant region pattern for a liquid crystal display apparatus and a method for fabricating the same. The method comprises providing a first substrate and a second substrate opposite thereto, forming a predetermined material layer on the first substrate, forming an organic material pattern layer having openings of a saw tooth pattern on the predetermined material layer to expose the surface of the predetermined material layer underneath, The surface of the predetermined material layer and the sidewall of the organic material pattern layer form a predetermined angle.

Abstract: The present invention discloses a membrane zeta potential measuring system which comprises a first measuring course and a second measuring course. The provided system calculates the zeta potential of the membrane pores based on a first potential drop measured from the first measuring course, and calculates the zeta potential of the membrane surface based on a second potential drop measured from the second measuring course.