Abstract: A keyboard device includes a light guide plate, a base plate, plural keys and plural surround-type soundproof elements. The base plate is located over the light guide plate. The plural keys are connected with the base plate. The membrane circuit board is arranged between the plural keys and the base plate. The plural surround-type soundproof elements are aligned with the corresponding keys. Each surround-type soundproof element is disposed on the light guide plate, the base plate or the membrane circuit board. While one of the plural keycaps is depressed and moved downwardly relative to the base plate, a sealed space is defined by the corresponding keycap and the corresponding surround-type soundproof element.

Abstract: A keyboard device includes a light guide plate, a base plate, plural keys and plural surround-type soundproof elements. The base plate is located over the light guide plate. The plural keys are connected with the base plate. The membrane circuit board is arranged between the plural keys and the base plate. The plural surround-type soundproof elements are aligned with the corresponding keys. Each surround-type soundproof element is disposed on the light guide plate, the base plate or the membrane circuit board. While one of the plural keycaps is depressed and moved downwardly relative to the base plate, a sealed space is defined by the corresponding keycap and the corresponding surround-type soundproof element.

Abstract: A scissors-type connecting member includes a first frame and a second frame. The first frame includes a rotating shaft. The second frame includes a pivot hole, an entrance and a stopper. After the rotating shaft is introduced into the pivot hole through the entrance, the first frame is pivotally coupled to the second frame. The stopper is located near the entrance or arranged between the entrance and the pivot hole. A position of the rotating shaft is limited between the stopper and the pivotal hole by the stopper. Consequently, the scissors-type connecting member is assembled easily, and the stability of connecting a first frame and a second frame of the scissors-type connecting member is enhanced. Moreover, the present invention also provides a key structure with the scissors-type connecting member.

Abstract: A supporting mechanism for an electronic device includes a base, a fixing plate, a supporting frame and a rotating module. The fixing plate can receive the electronic device. The fixing plate is placed on the base and rotatable relative to the base. The supporting frame is placed on the fixing plate and rotatable relative to the fixing plate. The rotating module is connected with the base, the fixing plate and the supporting frame. After the fixing plate is rotated relative to the base and the supporting frame is moved with the fixing plate by a predetermined angle, the supporting frame is rotated relative to the fixing plate but not synchronously rotated with the fixing plate according to the operation of the rotating module. By simply uplifting or covering the fixing plate and not operating the supporting frame, the electronic device can be controlled as required.

Abstract: A scissors-type connecting member includes a first frame and a second frame. The first frame includes a rotating shaft. The second frame includes a pivot hole, an entrance and a stopper. After the rotating shaft is introduced into the pivot hole through the entrance, the first frame is pivotally coupled to the second frame. The stopper is located near the entrance or arranged between the entrance and the pivot hole. A position of the rotating shaft is limited between the stopper and the pivotal hole by the stopper. Consequently, the scissors-type connecting member is assembled easily, and the stability of connecting a first frame and a second frame of the scissors-type connecting member is enhanced. Moreover, the present invention also provides a key structure with the scissors-type connecting member.

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: A handheld electronic device including a main body, a display unit and a press-type keyboard is provided. The main body has a data process module, and the display unit is mounted on the main body. The press-type keyboard having a center and a plurality of keys is mounted on the main body and adjacent to the display unit. Moreover, the closer each key is to the center, the higher the apex of the key is protruding above the main body. Because the height of the keys varies with the distance between the keys and the center, it is more convenient for users when keying in data.

Abstract: A recordable optical disc and a method for manufacturing a mother disc thereof are proposed. The recordable optical disc comprises a substrate with a spiral groove wobbled in a fixed period. The recordable optical disc is characterized in that the spiral groove has a plurality of transient side-wobble regions not in the wobble period and used as recording regions of address data. In the method of manufacturing a mother disc of the optical disc, a spiral groove is first formed on a mother disc substrate by using an etching source wobbling in a fixed period. A transient side-wobble not in the wobble period is inserted between several wobble periods to form a spiral groove having transient side-wobble regions on the mother disc substrate. The stability of manufacture of the mother disc can thus be greatly enhanced, and the PI error rate of the optical disc can be lowered.

Abstract: The present invention discloses a film structure of a rewritable compact disc including a transparent substrate on which sequentially laminated a phase-change recording layer, a dielectric layer and a reflective layer; and a barrier layer located between the dielectric layer and the reflective layer to insulate the dielectric layer and the reflective layer, and the feature of the barrier layer is that the barrier layer is composed of a germanium compound. The present invention provides an easily controlled process of the film structure, which can effectively improve the weather-resistibility of the disc to extend the lifetime and the conserving time of the disc.

Abstract: A heat-dissipating device is adapted for use with a multi-layer circuit board having a grounding layer and that has an electronic component mounted thereon. The heat-dissipating device includes a heat-dissipating member, a grounding member and a connecting member. The heat-dissipating member is adapted to be disposed on a heat-radiating side of the electronic component. The grounding member includes a grounding tail and a grounding body connected to the grounding tail. The grounding tail is adapted to pass through the circuit board to connect electrically with the grounding layer and to dispose the grounding body between the heat-dissipating member and the circuit board. The connecting member interconnects the heat-dissipating member and the grounding member, and is adapted to be secured on the circuit board. The connecting member cooperates with the grounding member to make electrical connection between the heat-dissipating member and the grounding layer of the circuit board.