Patents by Inventor Yi-Chen Tseng

Yi-Chen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12720073
    Abstract: The present invention provides an encoding method, which includes steps of: determining a first quantization parameter of a first superblock of an image frame; determining a binary code for the first superblock; determining whether binary code information of the first superblock is greater than a first threshold; and if the binary code information of the first superblock is greater than the first threshold, increasing a second quantization parameter of a second superblock.
    Type: Grant
    Filed: January 17, 2025
    Date of Patent: August 25, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Wei Li, Weimin Zeng, Chi-Wang Chai, Wujun Chen
  • Publication number: 20260214239
    Abstract: The present invention provides an encoding method, which includes steps of: determining a first quantization parameter of a first superblock of an image frame; determining a binary code for the first superblock; determining whether binary code information of the first superblock is greater than a first threshold; and if the binary code information of the first superblock is greater than the first threshold, increasing a second quantization parameter of a second superblock.
    Type: Application
    Filed: January 17, 2025
    Publication date: July 23, 2026
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Wei Li, Weimin Zeng, Chi-Wang Chai, Wujun Chen
  • Publication number: 20260214230
    Abstract: The present invention provides an encoder including M core circuits. The M core circuits are configured to encode a first row of superblocks to a M-th row of superblocks of an image frame, and to update a cumulative distribution function (CDF) table during an encoding process of each superblock, where M is a positive integer greater than 1. The M core circuits are further configured to encode a (M+1)-th row of superblocks to a (2*M)-th row of superblocks of the image frame, and to update the CDF table during the encoding process of each superblock, wherein a first core circuit of the M core circuits uses the CDF table generated during the encoding process of a last superblock of the first row of superblocks to encode a first superblock of the (M+1)-th row of superblocks.
    Type: Application
    Filed: January 17, 2025
    Publication date: July 23, 2026
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Wei Li, Weimin Zeng, Chi-Wang Chai, Wujun Chen
  • Patent number: 12598318
    Abstract: A method for performing memory access control with limited search range size during video encoding includes: loading partial data of non-encoded video data corresponding to a picture into a search memory of a video processing circuit for performing at least one motion estimation (ME) operation of the video encoding; and configuring at least one ME search range corresponding to at least one ME region within memory space of the search memory for performing the at least one ME operation, wherein the at least one ME search range includes the at least one ME region, and the video processing circuit is arranged to perform the at least one ME operation with an extended search range greater than the at least one ME search range in the memory space for enhancing ME performance.
    Type: Grant
    Filed: November 3, 2024
    Date of Patent: April 7, 2026
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yi-Chen Tseng
  • Publication number: 20250317586
    Abstract: A method for performing memory access control with limited search range size during video encoding includes: loading partial data of non-encoded video data corresponding to a picture into a search memory of a video processing circuit for performing at least one motion estimation (ME) operation of the video encoding; and configuring at least one ME search range corresponding to at least one ME region within memory space of the search memory for performing the at least one ME operation, wherein the at least one ME search range includes the at least one ME region, and the video processing circuit is arranged to perform the at least one ME operation with an extended search range greater than the at least one ME search range in the memory space for enhancing ME performance.
    Type: Application
    Filed: November 3, 2024
    Publication date: October 9, 2025
    Applicant: Realtek Semiconductor Corp.
    Inventor: Yi-Chen Tseng
  • Patent number: 12363330
    Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 15, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Po-Hsien Wu
  • Patent number: 12262057
    Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 25, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
  • Publication number: 20240048740
    Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.
    Type: Application
    Filed: April 17, 2023
    Publication date: February 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Po-Hsien Wu
  • Publication number: 20240048734
    Abstract: An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.
    Type: Application
    Filed: April 17, 2023
    Publication date: February 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Po-Hsien Wu, Yi-Chen Tseng
  • Publication number: 20230418560
    Abstract: The present invention discloses a computation circuit. Each of a first and a second term computation circuits includes higher bit computation circuits, a lowest bit computation circuit and a first adder. Each of the higher bit computation circuits left-shifts a multiplier, outputs the effective shifted multiplier having a sign determined and further performs left-shifts without performing 2's complement computation to generate a higher bit computation result. The lowest bit computation circuit outputs the effective multiplier having the sign determined to generate a lowest bit computation result. The first adder adds the bit computation results to generate a term computation result. The third term computation circuit outputs an effective addend having the sign determined and adds the addend to the summation of a number of 2's complement to generate a third term computation result. The second adder adds the term computation results and the third term computation result to generate a total computation result.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 28, 2023
    Inventors: SZU-CHUN CHANG, YI-CHEN TSENG
  • Publication number: 20230308687
    Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng
  • Publication number: 20220071344
    Abstract: A sole structure includes: an anti-skid layer, a rigid layer, an elastic piece and a soft layer which are superimposed upon one another. With the characteristic of the elastic piece being elastically deformable, a rebounding force can be produced to act on the foot to stimulate the ligaments and muscles of the foot, which consequently corrects flatfootedness.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 10, 2022
    Inventor: Yi-Chen TSENG
  • Patent number: 11087427
    Abstract: A method for dynamically limiting a memory bandwidth of a graphics processing unit (GPU) is applicable to a bandwidth-limited system. The bandwidth-limited system includes an audio/video decoder and a GPU. The method includes detecting a plurality of decoding times of a plurality of frames of an audio/video decoded by an audio/video decoder, and adjusting a max grant amount of a memory bandwidth of a GPU according to the plurality of decoding times of the plurality of frames and a target time. Therefore, in the case where the total memory bandwidth is limited, the memory bandwidth of the GPU is limited by the performance of the corresponding audio/video decoder such that, during audio/video playback, the effect of audio/video playback can be prevented from being affected and at the same time a better graphical user interface can be provided.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 10, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Chen Tseng, Ming-Yang Tseng
  • Publication number: 20200168307
    Abstract: Provided herein is to a blockchain-implemented method and a system for accessing electronic medical and health records by blockchain. The method is operated in a server system that is used to manage one or more medical-health record databases and users' blockchain IDs. The plurality of medical-health record databases can be set by different medical-health institutions. The server system identifies the user's blockchain ID when it receives a request from a terminal device. The user uses a query interface to generate a query command. The server system then obtains one or more medical-health record indexes via blockchain verification according to the user's blockchain ID and the query command. The medical-health records corresponding to the indexes can therefore be obtained after querying the database.
    Type: Application
    Filed: November 28, 2019
    Publication date: May 28, 2020
    Inventors: Ray-Jade Chen, Yu-Sheng Lo, Lan-Ying Kang, Christine Chen, Yi-Chen Tseng
  • Publication number: 20190269200
    Abstract: A sole structure includes: an anti-skid layer, a rigid layer, an elastic piece and a soft layer which are superimposed upon one another. With the characteristic of the elastic piece being elastically deformable, a rebounding force can be produced to act on the foot to stimulate the ligaments and muscles of the foot, which consequently corrects the flatfoot.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventor: Yi-Chen TSENG
  • Publication number: 20190272611
    Abstract: A method for dynamically limiting a memory bandwidth of a graphics processing unit (GPU) is applicable to a bandwidth-limited system. The bandwidth-limited system includes an audio/video decoder and a GPU. The method includes detecting a plurality of decoding times of a plurality of frames of an audio/video decoded by an audio/video decoder, and adjusting a max grant amount of a memory bandwidth of a GPU according to the plurality of decoding times of the plurality of frames and a target time. Therefore, in the case where the total memory bandwidth is limited, the memory bandwidth of the GPU is limited by the performance of the corresponding audio/video decoder such that, during audio/video playback, the effect of audio/video playback can be prevented from being affected and at the same time a better graphical user interface can be provided.
    Type: Application
    Filed: August 3, 2018
    Publication date: September 5, 2019
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Chen Tseng, Ming-Yang Tseng
  • Patent number: 10258147
    Abstract: A lifting device for lifting a table includes two legs, each of the legs includes a pneumatic assembly and an inner rod, the pneumatic assemblies are disposed in the legs, and the inner rods are inserted in the legs and connected to the pneumatic assemblies, so that the pneumatic assemblies drive the inner rods to move up and down. A synchronization mechanism is disposed between the two legs, and has two ends connected to the inner rods by two connecting assemblies, so that the inner rods are driven by the synchronization mechanism to lift or lower the tabletop in a synchronous manner, the synchronization mechanism includes: a cable control unit and a clutch unit controlled by the cable control unit, the cable control unit includes a control handle and a cable which is disposed at the bottom of the tabletop.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 16, 2019
    Assignees: Hi-Max Innovation Co., Ltd.
    Inventor: Yi-Chen Tseng
  • Publication number: 20180071132
    Abstract: A mat structure includes: an anti-skid layer, a rigid layer, and a soft layer which are superimposed upon one another. A plurality of stimulating protrusions is disposed between the rigid layer and the soft layer to stimulate the ligament and muscle of the foot, which can consequently correct the flatfoot.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 15, 2018
    Inventor: Yi-Chen Tseng
  • Publication number: 20180064241
    Abstract: A lifting device for lifting a table includes two legs, each of the legs includes a pneumatic assembly and an inner rod, the pneumatic assemblies are disposed in the legs, and the inner rods are inserted in the legs and connected to the pneumatic assemblies, so that the pneumatic assemblies drive the inner rods to move up and down. A synchronization mechanism is disposed between the two legs, and has two ends connected to the inner rods by two connecting assemblies, so that the inner rods are driven by the synchronization mechanism to lift or lower the tabletop in a synchronous manner, the synchronization mechanism includes: a cable control unit and a clutch unit controlled by the cable control unit, the cable control unit includes a control handle and a cable which is disposed at the bottom of the tabletop.
    Type: Application
    Filed: October 14, 2016
    Publication date: March 8, 2018
    Inventor: Yi-Chen Tseng
  • Patent number: D812947
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 20, 2018
    Assignees: Hi-Max Innovation Co., Ltd.
    Inventor: Yi-Chen Tseng