Patents by Inventor Yi-Cheng CHIU

Yi-Cheng CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159334
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun Lin Tsai
  • Patent number: 11018170
    Abstract: An image sensor includes a pair of pixel sharing circuits, a second reset transistor, an amplifier transistor, a readout transistor and a control circuit. The pair of pixel sharing circuits connected to a floating diffusion node, each including a photon device, a first reset transistor, a capture transistor, a holding transistor, a capacitor and a sharing transistor. The control circuit is configured to control the first reset transistor, the first capture transistor, the first holding transistor and the sharing transistor of each of the pair of sharing pixel circuits to be turned on or off.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 25, 2021
    Assignee: PIXART IMAGING INC.
    Inventors: Kuan Tang, Jui-Te Chiu, Yi-Cheng Chiu, Chia-Chi Kuo, Kai-Chieh Chuang
  • Patent number: 11012653
    Abstract: A method of image sensor apparatus includes: providing pixel array having pixel units arranged in M rows and N columns; providing N parallel column readout circuits each being arranged for reading out pixel data of one corresponding column; disposing a horizontal shift register in row direction coupled to the N parallel column readout circuits, to receive a pulse signal and a clock signal, sequentially shift a phase of the pulse signal according to the clock signal, and scan a corresponding column according to the shifted phase of the pulse signal; and using a column select circuit having N latches to receive a power down digital control signal transmitted from a microcontroller wherein the power down digital control signal is used to disable at least one column readout circuit to enable and select a portion of the set of N parallel column readout circuits.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 18, 2021
    Assignee: PixArt Imaging Inc.
    Inventors: Chia-Chi Kuo, Jui-Te Chiu, Han-Chi Liu, Wei-Chia Huang, Yi-Cheng Chiu, Kuan Tang
  • Patent number: 10999549
    Abstract: A column parallel ADC circuit includes: plural column ADCs and a digital processing circuit. The plural column ADCs generate respective plural digital counts. The plural column ADCs include a first column ADC and a second column ADC. The first column ADC generates a first digital count according to a first analog signal, and the second column ADC generates a second digital count according to a second analog signal. The first digital count is a difference between a first digital signal and a second digital signal. The first and the second digital signals correspond to the first and the second analog signals respectively. The digital processing circuit generates the plural digital signals, wherein the digital processing circuit generates the first digital signal according to the first digital count and the second digital signal.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: May 4, 2021
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Kuan Tang, Yi-Cheng Chiu, Chia-Chi Kuo, Jui-Te Chiu
  • Publication number: 20210112215
    Abstract: A method of image sensor apparatus includes: providing pixel array having pixel units arranged in M rows and N columns; providing N parallel column readout circuits each being arranged for reading out pixel data of one corresponding column; disposing a horizontal shift register in row direction coupled to the N parallel column readout circuits, to receive a pulse signal and a clock signal, sequentially shift a phase of the pulse signal according to the clock signal, and scan a corresponding column according to the shifted phase of the pulse signal; and using a column select circuit having N latches to receive a power down digital control signal transmitted from a microcontroller wherein the power down digital control signal is used to disable at least one column readout circuit to enable and select a portion of the set of N parallel column readout circuits.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Inventors: Chia-Chi Kuo, Jui-Te Chiu, Han-Chi Liu, Wei-Chia Huang, Yi-Cheng Chiu, Kuan Tang
  • Patent number: 10964781
    Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Cheng Chiu, Wen-Chih Chiang, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Karthick Murukesan
  • Patent number: 10892360
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: January 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20200411571
    Abstract: An image sensor includes a pair of pixel sharing circuits, a second reset transistor, an amplifier transistor, a readout transistor and a control circuit. The pair of pixel sharing circuits connected to a floating diffusion node, each including a photon device, a first reset transistor, a capture transistor, a holding transistor, a capacitor and a sharing transistor. The control circuit is configured to control the first reset transistor, the first capture transistor, the first holding transistor and the sharing transistor of each of the pair of sharing pixel circuits to be turned on or off.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: KUAN TANG, JUI-TE CHIU, YI-CHENG CHIU, CHIA-CHI KUO, KAI-CHIEH CHUANG
  • Patent number: 10879236
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200404205
    Abstract: A column parallel ADC circuit includes: plural column ADCs and a digital processing circuit. The plural column ADCs generate respective plural digital counts. The plural column ADCs include a first column ADC and a second column ADC. The first column ADC generates a first digital count according to a first analog signal, and the second column ADC generates a second digital count according to a second analog signal. The first digital count is a difference between a first digital signal and a second digital signal. The first and the second digital signals correspond to the first and the second analog signals respectively. The digital processing circuit generates the plural digital signals, wherein the digital processing circuit generates the first digital signal according to the first digital count and the second digital signal.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: KUAN TANG, YI-CHENG CHIU, CHIA-CHI KUO, JUI-TE CHIU
  • Publication number: 20200302151
    Abstract: An event detection device includes a sensor array and a processor. The sensor array is adapted to capture one image. The processor is electrically connected with the sensor array. The processor is adapted to identify if the captured image contains a specific pattern, and trigger an external device to determine whether the specific pattern matches a predetermined feature when the captured image contains the specific pattern.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Han-Chang Lin, Han-Chi Liu, Yi-Cheng Chiu
  • Patent number: 10679987
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200105864
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: June 12, 2019
    Publication date: April 2, 2020
    Inventors: Hong-Yang CHEN, Tian Sheng LIN, Yi-Cheng CHIU, Hung-Chou LIN, Yi-Min CHEN, Kuo-Ming WU, Chiu-Hua CHUNG
  • Patent number: 10609319
    Abstract: An image sensor including a first pixel circuit, a second pixel circuit, a first readout line, a second readout line, a first readout circuit, a second readout circuit and an average switch is provided. The first and second pixel circuits are in two columns of a pixel array. The first readout line transmits pixel data of the first pixel circuit to the first readout circuit. The second readout line transmits pixel data of the second pixel circuit to the second readout circuit. The average switch is arranged between the first and second readout lines and used to electrically connect the first and second readout lines in an average mode to average the pixel data on the first and second readout lines.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 31, 2020
    Assignee: PIXART IMAGING INC.
    Inventors: Chia-Chi Kuo, Jui-Te Chiu, Han-Chi Liu, Peng-Sheng Chen, Yi-Cheng Chiu
  • Publication number: 20200058647
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200044014
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 10535730
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20190360863
    Abstract: There is provided a circuit to improve the sensing efficiency of pixels that uses the induction effect of a capacitor to duplicate a voltage deviation caused by additional electrons and uses a circuit to cancel out the voltage deviation during reading pixel data thereby improving the sensing efficiency.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 28, 2019
    Inventors: Kuan TANG, Yi-Cheng CHIU, Chia-Chi KUO, Jui-Te CHIU, Han-Chi LIU
  • Publication number: 20190174084
    Abstract: An image sensor including a first pixel circuit, a second pixel circuit, a first readout line, a second readout line, a first readout circuit, a second readout circuit and an average switch is provided. The first and second pixel circuits are in two columns of a pixel array. The first readout line transmits pixel data of the first pixel circuit to the first readout circuit. The second readout line transmits pixel data of the second pixel circuit to the second readout circuit. The average switch is arranged between the first and second readout lines and used to electrically connect the first and second readout lines in an average mode to average the pixel data on the first and second readout lines.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Chia-Chi KUO, Jui-Te CHIU, Han-Chi LIU, Peng-Sheng CHEN, Yi-Cheng CHIU
  • Publication number: 20190165167
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chou LIN, Yi-Cheng CHIU, Karthick MURUKESAN, Yi-Min CHEN, Shiuan-Jeng LIN, Wen-Chih CHIANG, Chen-Chien CHANG, Chih-Yuan CHAN, Kuo-Ming WU, Chun-Lin TSAI