Abstract: In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Abstract: Methods for forming a semiconductor device structure are described. The method includes forming first and second fin structures over a substrate and forming a dielectric wall between the first and second fin structures. The forming the dielectric wall includes depositing a first dielectric layer between the first and second fin structures, and a seam is formed in the first dielectric layer. The forming the dielectric wall further includes performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam, performing an isotropic etch process to enlarge an opening of the seam, and the seam has a “V” shaped cross-sectional profile. The forming the dielectric wall further includes depositing a second dielectric layer between the first and second fin structures, and the seam is filled. The method further includes forming shallow trench isolation regions adjacent the first and second fin structures.

Abstract: The present invention relates methods for treating thyroid cancer, renal cell carcinoma or hepatocellar carcinoma comprising orally administering to a patient in need of such therapy a therapeutic amount of cabozantinib lauryl sulfate salt, preferably in a capsule form. The method allows the administration of the therapeutic amount of cabozantinib lauryl sulfate salt in a fed state or a fasted state and the administration does not exhibit a food effect.

Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent resistor. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates a resistance of the resonant tank equivalent resistor according to the inductance of the resonant tank equivalent inductor, a time change value, a reference voltage value, a negative peak voltage value and a second expression.

Abstract: The present invention relates methods for treating thyroid cancer, renal cell carcinoma or hepatocellar carcinoma comprising orally administering to a patient in need of such therapy a therapeutic amount of cabozantinib lauryl sulfate salt, preferably in a capsule form. The method allows the administration of the therapeutic amount of cabozantinib lauryl sulfate salt in a fed state or a fasted state and the administration does not exhibit a food effect.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: An optical lens system includes six lens elements from an object side to an image side, the six lens elements are, in order from the object side to the image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The image-side surface of the second lens element is concave in a paraxial region thereof. The third lens element has positive refractive power. The image-side surface of the fourth lens element is concave in a paraxial region thereof. The image-side surface of the sixth lens element includes at least one inflection point.

Abstract: The present invention is a reconfigurable antenna, which includes a total reflection part, a partial reflection part, a partial transmission part, and a radiation part stacked in sequence. A resonant cavity is formed between the partial reflection part and the total reflection part. The radiation part is arranged in the resonant cavity. So that the electromagnetic wave radiated by the radiation part is reflected in the resonant cavity. The electromagnetic wave forms constructive interference during the reflection of the resonant cavity. The resonant cavity makes the electromagnetic wave form the same phase electromagnetic wave and radiation penetrating the reflection part. The partial transmission part is regulated to form beam reconstruction conditions, and the same-phase electromagnetic waves are formed into beams and radiated into space by the beam control conditions.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, a gate structure surrounding the nanostructured channel region, a source/drain (S/D) region disposed adjacent to the nanostructured channel region, an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the etch stop layer and configured to provide compressive stress in the nanostructured channel region, an inter-layer dielectric (ILD) layer disposed on the stress liner, and a contact structure disposed in the S/D region, ESL, stress liner, and ILD layer.

Abstract: Disclosed are a dual-polarization cavity-backed antenna, a package module and an array package module. The antenna includes a substrate, a magnetic current feeding structure, an electric current feeding structure, and a cavity-backed structure that is arranged between two surfaces of the substrate. The magnetic current feeding structure and the electric current feeding structure transfer energy into the cavity-backed structure, respectively radiating the orthogonally polarized electromagnetic wave. The electric field direction of the first electromagnetic wave and the magnetic field direction of the second electromagnetic wave occur on the same plane. The package module includes the dual-polarization cavity-backed antenna, a radio frequency control chip, and a control circuit unit. The array package module includes a plurality of the dual-polarization cavity-backed antennas, a radio frequency control unit including a single RF chip or chip set, and a control circuit unit.

Abstract: A planarization tool is configured to monitor and analyze the condition of a polishing pad over the life of the polishing pad. A piezoelectric pad monitoring device may be mounted to a polishing head of the planarization tool in place of a semiconductor wafer. The piezoelectric pad monitoring device may be pressed against the polishing pad. When pressed against the polishing pad, the piezoelectric pad monitoring device may generate a signal based on a quantity of pad contacts, on the polishing pad, that are in contact with the piezoelectric pad monitoring device. The signal may be provided to a processor of the planarization tool so that the processor may generate, based on the signal, a map of the pad contacts on the polishing pad. The processor may use the map of the pad contacts to determine properties of the polishing pad such as roughness and/or uniformity, among other examples.

Abstract: A light guide element includes first and second surfaces, a light-incident surface, and microstructure groups arranged on the first surface. Each microstructure group includes a first microstructure and a second microstructure separated from and being mirror image structures of each other. A first intersection line is provided between a first light-receiving surface of the first microstructure and the first surface. A first distance is provided between the first intersection line and a light-incident intersection line in a first direction. A second intersection line is provided between a second light-receiving surface of the second microstructure and the first surface. A second distance is provided between the second intersection line and the light-incident intersection line in the first direction. A variation trend of the first distance in a second direction is opposite to a variation trend of the second distance in the second direction.

Abstract: A display apparatus, including a first electrically controlled liquid crystal cell and a second electrically controlled liquid crystal cell, is proposed. The first electrically controlled liquid crystal cell includes a first substrate, a second substrate, a first liquid crystal layer, and a touch electrode layer. The first liquid crystal layer and the touch electrode layer are disposed between the first substrate and the second substrate. The second electrically controlled liquid crystal cell is disposed on one side of the first substrate of the first electrically controlled liquid crystal cell and overlapping the first electrically controlled liquid crystal cell. A spacer layer or a conductive layer is disposed between the first electrically controlled liquid crystal cell and the second electrically controlled liquid crystal cell, and the spacer layer or the conductive layer is disposed on a surface of the first substrate facing away from the first liquid crystal layer.

Abstract: An electrode structure on a circuit board, the electrode structure comprising a metal structure disposed on and electrically connected to the circuit board, wherein the metal structure and a surface of the circuit board forms a space therebetween, wherein at least one first electrical component is disposed in the space and an outer surface of the metal structure forms an electrode for electrically connecting with an external component.

Abstract: A display apparatus having a privacy mode and a sharing mode is provided. The display apparatus includes a display panel, a privacy liquid crystal module, and a touch sensing module. The touch sensing module is disposed on a side of the privacy liquid crystal module and is configured to generate a touch signal. When the display apparatus is in the privacy mode, the privacy liquid crystal module is applied with a first voltage. When the display apparatus is in the sharing mode and the touch sensing module generates the touch signal, the privacy liquid crystal module is applied with a second voltage for a predetermined time. After maintaining for the predetermined time, a third voltage is applied to the privacy liquid crystal module. The display apparatus can effectively reduce a smear phenomenon caused by the display apparatus being touched in a sharing mode.

Abstract: A 2D layered thin film structure is disclosed. The 2D layered thin film structure can be applied to the growth of monocrystalline or polycrystalline group III nitrides and other 2D materials. The 2D layered thin film structure can be easily separated from the 2D layered thin film structure growth substrate, so that a single or composite nanopillar array structure formed by the monocrystalline or polycrystalline group III nitride or other 2D materials, or the 2D layered thin film structure can be transferred to any other substrate. In addition, the 2D layered thin film structure has excellent light transmittance, flexibility and component integration.