Patents by Inventor Yi-Chi Huang
Yi-Chi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969447Abstract: A composition for promoting defecation includes a cell culture of at least one lactic acid bacterial strain which is substantially free of cells. The least one lactic acid bacterial strain is selected from the group consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9, and Lactobacillus acidophilus TYCA06, which are respectively deposited at the Bioresource Collection and Research Center (BCRC) under accession numbers BCRC 910437, BCRC 910645 and BCRC 910813. Also disclosed is a method for promoting defecation, including administering to a subject in need thereof an effective amount of the composition.Type: GrantFiled: March 17, 2021Date of Patent: April 30, 2024Assignee: GLAC BIOTECH CO., LTD.Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yi-Wei Kuo, Yu-Fen Huang, Cheng-Chi Lin
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Patent number: 11933946Abstract: An optical imaging lens includes first, second, third, fourth, fifth, and sixth lens elements sequentially along an optical axis from an object side to an image side. Each of the first to the sixth lens elements includes an object-side surface facing the object side and allowing imaging rays to pass through and an image-side surface facing the image side and allowing the imaging rays to pass through. The optical imaging lens satisfies conditions of Gallmax/Fno?3.600 millimeters, EFL/ImgH?3.200, and Gallmax/Tavg?3.300; here, Gallmax represents a largest air gap along the optical axis between the first lens element and an image plane, Fno, EFL, and ImgH respectively represent an F-number, an effective focal length, and an image height of the optical imaging lens, and Tavg represents an average lens element thickness of all of the lens elements along the optical axis from the object side to the image plane.Type: GrantFiled: July 27, 2020Date of Patent: March 19, 2024Assignee: GENIUS ELECTRONIC OPTICAL (XIAMEN) CO., LTD.Inventors: Pei-Chi Wang, Yi-Ling Huang
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Patent number: 11715639Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.Type: GrantFiled: September 12, 2017Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Chun Sie, Po-Yi Tseng, Chien-Hao Chen, Ching-Lun Lai, David Sung, Ming-Feng Hsieh, Yi-Chi Huang
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Patent number: 10930527Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.Type: GrantFiled: June 12, 2020Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
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Publication number: 20200312685Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.Type: ApplicationFiled: June 12, 2020Publication date: October 1, 2020Inventors: Jian-Lun LO, Jih-Churng TWU, Feng-Yu CHEN, Yuan-Hsiao SU, Yi-Chi HUANG, Yueh-Ting YANG, Shu-Han CHAO
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Patent number: 10741426Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.Type: GrantFiled: February 27, 2018Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
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Publication number: 20200218365Abstract: A method of motion capture includes: by multiple positioning devices located on a user, receiving scanning signals emitted by signal emitting devices to obtain detected coordinates, determining angular information, and generating and transmitting to a processor position signals that contain the angular information and the detected coordinates of the positioning devices; by the processor based on the position signals and data of a skeleton related to the user, determining estimated coordinates of a position of a body portion of the user; and generating an image of a virtual object based on the position signals, the estimated coordinates, the data of the skeleton related to the user and data of a skeleton related to a virtual object, and controlling a display to display the image.Type: ApplicationFiled: December 31, 2019Publication date: July 9, 2020Inventors: Dobromir Todorov, Yi-Chi Huang, Ting-Chieh Lin, Chien-Hung Shih
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Patent number: 10539811Abstract: Eyeglasses having a hidden pivot structure include a frame and two temples. The frame has a first inner surface and a first outer surface. Two sides of the frame have first end surfaces, respectively. The first end surfaces are adjacent to the first inner surface and the first outer surface, respectively. Each first end face is formed with two engaging recesses. The engaging recesses are connected to the first inner surface. The two temples are pivotally connected to the frame. Each temple has a second inner surface and a second outer surface. Each temple has a second end surface. The second end surface is adjacent to the second inner surface and the second outer surface. The second end face is formed with two engaging blocks. When the two temples are unfolded relative to the frame, the engaging blocks are engaged in the engaging recesses, respectively.Type: GrantFiled: February 21, 2018Date of Patent: January 21, 2020Inventor: Yi-Chi Huang
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Publication number: 20190258078Abstract: Eyeglasses having a hidden pivot structure include a frame and two temples. The frame has a first inner surface and a first outer surface. Two sides of the frame have first end surfaces, respectively. The first end surfaces are adjacent to the first inner surface and the first outer surface, respectively. Each first end face is formed with two engaging recesses. The engaging recesses are connected to the first inner surface. The two temples are pivotally connected to the frame. Each temple has a second inner surface and a second outer surface. Each temple has a second end surface. The second end surface is adjacent to the second inner surface and the second outer surface. The second end face is formed with two engaging blocks. When the two temples are unfolded relative to the frame, the engaging blocks are engaged in the engaging recesses, respectively.Type: ApplicationFiled: February 21, 2018Publication date: August 22, 2019Inventor: YI-CHI HUANG
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Publication number: 20190096714Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.Type: ApplicationFiled: February 27, 2018Publication date: March 28, 2019Inventors: Jian-Lun LO, Jih-Churng TWU, Feng-Yu CHEN, Yuan-Hsiao SU, Yi-Chi HUANG, Yueh-Ting YANG, Shu-Han CHAO
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Publication number: 20180151372Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.Type: ApplicationFiled: September 12, 2017Publication date: May 31, 2018Inventors: Yuan-Chun SIE, Po-Yi TSENG, Chien-Hao CHEN, Ching-Lun LAI, David SUNG, Ming-Feng HSIEH, Yi-Chi HUANG
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Patent number: 7827540Abstract: A method for program debugging includes setting a plurality of breakpoints corresponding to a plurality of events in an implementation under test, executing the implementation under test for outputting a diagnosis code of a breakpoint, resetting a parameter of the event corresponding to the diagnosis code, and executing the event according to the reset parameter for making the event undergo an error handler. The method helps execute functions of error handlers and execute a test completely.Type: GrantFiled: February 11, 2004Date of Patent: November 2, 2010Assignee: Micro-Star Int'l Co., Ltd.Inventors: Hsiu-Chuan Lien, Hai-Yu Tseng, legal representative, Yi-Chi Huang, Ko-Pin Huang
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Patent number: 7039797Abstract: A method of allocating a basic input/output system to a shadow memory applied to a computer including a plurality of equipment having an operation read only memory and a shadow memory. The method includes executing the preliminary initialization of the equipment to acquire the capacity of the operation read only memory of each equipment after being initialized. Then the equipment is re-initialized according to the order of the capacity of each operation read only memory after being initialized from smallest capacity to largest capacity to allocate the shadow memory more effectively and increase the number of equipment to be enabled.Type: GrantFiled: June 17, 2003Date of Patent: May 2, 2006Assignee: Micro-Star Int'l Co., Ltd.Inventors: Yi-Chi Huang, Yang-Ning Lien
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Publication number: 20040194067Abstract: A method for program debugging includes setting a plurality of breakpoints corresponding to a plurality of events in an implementation under test, executing the implementation under test for outputting a diagnosis code of a breakpoint, resetting a parameter of the event corresponding to the diagnosis code, and executing the event according to the reset parameter for making the event undergo an error handler. The method helps execute functions of error handlers and execute a test completely.Type: ApplicationFiled: February 11, 2004Publication date: September 30, 2004Inventors: Hsiu-Chuan Lien, Hai-Yu Tseng, Yi-Chi Huang, Ko-Pin Huang
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Publication number: 20040186986Abstract: A method of allocating a basic input/output system to a shadow memory applied to a computer including a plurality of equipment having an operation read only memory and a shadow memory. The method includes executing the preliminary initialization of the equipment to acquire the capacity of the operation read only memory of each equipment after being initialized. Then the equipment is re-initialized according to the order of the capacity of each operation read only memory after being initialized from smallest capacity to largest capacity to allocate the shadow memory more effectively and increase the number of equipment to be enabled.Type: ApplicationFiled: June 17, 2003Publication date: September 23, 2004Inventors: Yi-Chi Huang, Yang-Ning Lien
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Patent number: D983174Type: GrantFiled: November 16, 2020Date of Patent: April 11, 2023Assignee: 3M Innovative Properties CompanyInventors: William P. Atwood, Yi-Chi Huang, Jeffrey L. Hamer, Paul D. Henry
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Patent number: D993165Type: GrantFiled: November 16, 2020Date of Patent: July 25, 2023Assignee: 3M Innovative Properties CompanyInventors: William P. Atwood, Yi-Chi Huang, Ravi Thomas, Jeffrey L. Hamer, Paul D. Henry
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Patent number: D1011321Type: GrantFiled: March 3, 2023Date of Patent: January 16, 2024Assignee: 3M Innovative Properties CompanyInventors: William Atwood, Yi-Chi Huang, Jeffrey L Hamer, Paul D. Henry