Patents by Inventor Yi-Chi Lin

Yi-Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240405414
    Abstract: An electronic device is provided. The electronic device includes a substrate and a plurality of units disposed on the substrate. A portion of the plurality of units includes a conductive layer and an insulating layer. The conductive layer has a first opening penetrating through the conductive layer. The insulating layer is disposed on the conductive layer and includes a second opening penetrating through the insulating layer. The first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped. Moreover, a width of the first opening of the conductive layer is greater than a width of the second opening of the insulating layer.
    Type: Application
    Filed: August 16, 2024
    Publication date: December 5, 2024
    Inventors: Yi-Hung LIN, Tang-Chin HUNG, Chia-Chi HO, I-Yin LI
  • Publication number: 20240395508
    Abstract: A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chung Chuan Huang, Yi-Tsang Hsieh, Yu-Chi Lin, Cha-Hsin Chao, Che-En Tsai
  • Publication number: 20240379421
    Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU
  • Patent number: 12142554
    Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: November 12, 2024
    Assignee: Innolux Corporation
    Inventors: Yeong-E Chen, Yi-Hung Lin, Cheng-En Cheng, Wen-Hsiang Liao, Cheng-Chi Wang
  • Publication number: 20240371868
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Patent number: 12131917
    Abstract: A manufacturing method of a package structure including the following steps is provided. A carrier is provided. An anti-warpage structure is formed on the carrier. And a redistribution layer is formed on the carrier. In the normal direction of the carrier, a warpage trend of the anti-warpage structure is opposite to a warpage trend of the redistribution layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: October 29, 2024
    Assignee: Innolux Corporation
    Inventors: Yi-Hung Lin, Wen-Hsiang Liao, Cheng-Chi Wang, Yi-Chen Chou, Fuh-Tsang Wu, Ker-Yih Kao
  • Patent number: 12131944
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Hsu, Chih-Chieh Chang, Yi-Sheng Lin, Jian-Ci Lin, Jeng-Chi Lin, Ting-Hsun Chang, Liang-Guang Chen, Ji Cui, Kei-Wei Chen, Chi-Jen Liu
  • Publication number: 20240352584
    Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hsuan WU, Teng Mao WANG, Yan-Chi PAN, Yi-Jiun SHIU, Jrjyan Jerry CHEN, Cheng-yuan LIN, Hsiao-Ling YANG, Yu-Min WANG, Wen-Hao WU
  • Patent number: 12125850
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Publication number: 20240332401
    Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240312836
    Abstract: A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yi-Hsiu Chen
  • Publication number: 20240312983
    Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, a PN junction assembly, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed above the second surface. The second metal layer is formed on the second surface. The PN junction assembly is disposed on the first surface and electrically connected with the first metal layer and the second metal layer. The PN junction assembly includes a variable capacitor. The transistor circuit is electrically connecting with the second metal layer.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Applicant: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • Patent number: 12095152
    Abstract: An electronic device is provided. The electronic device includes a substrate, a conductive layer, an insulating layer, and a modulating material. The conductive layer is disposed on the substrate and has a first opening penetrating through the conductive layer. The insulating layer is disposed on the conductive layer and includes a second opening penetrating through the insulating layer. The first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped. The modulating material is disposed on the insulating layer.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: September 17, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Hung Lin, Tang-Chin Hung, Chia-Chi Ho, I-Yin Li
  • Publication number: 20240297168
    Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes an insulator, a driving unit, an electronic unit, and a circuit unit. The driving unit is overlapped with the insulator. The electronic unit is overlapped with the insulator. The circuit unit is electrically connected to the driving unit. The driving unit receives a signal from the circuit unit and drives the electronic unit.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Applicant: Innolux Corporation
    Inventors: Tang Chin Hung, Chin-Lung Ting, Chung-Kuang Wei, Ker-Yih Kao, Tong-Jung Wang, Chih-Yung Hsieh, Hao Jung Huang, I-Yin Li, Chia-Chi Ho, Yi Hung Lin, Cheng-Hsu Chou, Chia-Ping Tseng
  • Patent number: 12074252
    Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: August 27, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chung-Hao Wang, Yu-Chi Wang, Yi-Ming Chen, Yi-Yang Chiu, Chun-Yu Lin
  • Publication number: 20240264405
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Inventors: Chao-Chang HU, Liang-Ting HO, Chen-Er HSU, Yi-Liang CHAN, Fu-Lai TSENG, Fu-Yuan WU, Chen-Chi KUO, Ying-Jen WANG, Wei-Han HSIA, Yi-Hsin TSENG, Wen-Chang LIN, Chun-Chia LIAO, Shou-Jen LIU, Chao-Chun CHANG, Yi-Chieh LIN, Shang-Yu HSU, Yu-Huai LIAO, Shih-Wei HUNG, Sin-Hong LIN, Kun-Shih LIN, Yu-Cheng LIN, Wen-Yen HUANG, Wei-Jhe SHEN, Chih-Shiang WU, Sin-Jhong SONG, Che-Hsiang CHIU, Sheng-Chang LIN
  • Patent number: 12050216
    Abstract: Disclosed herein are recombinant baculoviruses suitable for detecting the presence of arthropod-borne viruses in a biological sample of a test subject. The information derived from the detection may also be used to render a diagnosis on whether the test subject is infected with the arthropod-borne viruses or not, so that proper course of treatment may be assigned to the subject.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: July 30, 2024
    Assignee: Chung Yuan Christian University
    Inventors: Tzong-Yuan Wu, Szu-Cheng Kuo, Pei-Yun Shu, Chang-Chi Lin, Der-Jiang Chiao, Ying-Ju Chen, Yi-Ting Lin, Shu-Fen Chang, Chien-Ling Su
  • Patent number: 12040382
    Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11344053
    Abstract: An assisting apparatus for bean roasting and a bean roasting apparatus are provided. The present invention senses sound in a chamber of a bean roasting device through a microphone to generate an audio signal, and control the bean roasting procedure by determining that the energy value of the audio signal crosses a threshold at a time point based on the observation time window.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 31, 2022
    Assignee: JIYONSON CO., LTD.
    Inventors: Yun-Long Tun, Chia-Yen Liu, Yi-Chi Lin
  • Patent number: 11297874
    Abstract: An assisting apparatus for bean roasting and a bean roasting apparatus are provided. The assisting apparatus captures a scene in a chamber of the bean roasting device through an image capturing device to generate an image, compares the image with a historical roasting pattern set based on a plurality of color attributes of a color space to determine a roasting level represented by the image, and controls the bean roasting procedure.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 12, 2022
    Assignee: JIYONSON CO., LTD.
    Inventors: Yun-Long Tun, Chia-Yen Liu, Yi-Chi Lin