Patents by Inventor Yi Chiang
Yi Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178120Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.Type: ApplicationFiled: February 8, 2023Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
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Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
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Publication number: 20240178090Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.Type: ApplicationFiled: February 7, 2023Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Tzu-Sung Huang, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin
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Publication number: 20240178285Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A source electrode, a gate electrode and a drain electrode are disposed on the semiconductor channel layer. A patterned dielectric layer is disposed on the semiconductor barrier layer, and between the gate electrode and the drain electrode. A first field plate is extended continuously from a side of the patterned dielectric layer to the top surface thereof, and has a step in height. A first dielectric layer is disposed between the semiconductor barrier layer and the patterned dielectric layer. A second dielectric layer covers the patterned dielectric layer. The dielectric constant of the patterned dielectric layer is higher than that of the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: January 16, 2023Publication date: May 30, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Yi-Wei Lien, Wei-Chih Cheng, Shyh-Chiang Shen, Hsin-Chang Tsai
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Publication number: 20240175317Abstract: A blind lifting control module includes a transmitting wheel, an anti-backward unit and a driving unit disposed to a supporting unit. The transmitting wheel for connecting a blind reeled horizontal axle has a wheel ratchet portion meshable with a corresponding reel ratchet portion of a driving reel of the driving unit. The anti-backward unit has a torsion spring operable and deformable relative to the transmitting wheel. A pull cord is reeled on the driving reel and has a free end passing through a thrust member and a hindering member, and is pulled to shift the torsion spring to a released state to permit lowering of a blind. The thrust member is turned by pulling of the pull cord to thrust the driving reel to mesh with the transmitting wheel for lifting the blind.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Inventors: Cheng-Hung LEE, Lung-Yi CHIANG
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Patent number: 11994970Abstract: A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.Type: GrantFiled: January 5, 2021Date of Patent: May 28, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Kun-Hsin Chiang, Hsin-Hui Huang, Wei-Hsian Chang, Wen-Yen Hsieh, Ming-Yi Huang, Yu-Chieh Chang, Tang-Hui Liao, Chih-Wei Kuo
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Patent number: 11993512Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.Type: GrantFiled: March 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng, Yi-Chuan Teng
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Publication number: 20240170414Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.Type: ApplicationFiled: January 24, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsien Chiang, Hsien-Ming Tu, Hao-Yi Tsai, Tin-Hao Kuo
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Publication number: 20240166149Abstract: This disclosure is directed to a sunroof device having a window frame assembly, a pair of linkage assemblies, a panel assembly, a first electrical connector and a second electrical connector. The window frame assembly has a pair of rails. The linkage assemblies are disposed on the rails respectively. The panel assembly is disposed on the pair of linkage assemblies. The first electrical connector on the window frame assembly has a plugging slot and an opening, the opening is located at a side of the first electrical connector and extended to a top of the first electrical connector. The second electrical connector on the panel assembly has a conductive terminal. When the panel assembly rotates, the conductive terminal is plugged in the plugging slot through the opening and movable with the panel assembly in the opening.Type: ApplicationFiled: March 25, 2023Publication date: May 23, 2024Inventors: Chih-Wei LI, Sin-Hao HE, Yi-Jen LAN, Tzu-Chiang LEE, Jeng-Yin LAN
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Patent number: 11990578Abstract: A LED display structure and its display module thereof are provided. The LED display module includes a LED array, a substrate disposed below the LED array, and at least one trace configuration layer, which is disposed below the LED array and adjacent to the substrate. The at least one trace configuration layer includes a plurality of wires, and a distribution density of the wires varies according to a distance between the wires and the LED array. When the distance increases, the distribution density of the wires is denser. Otherwise, the distribution density is sparse when the wires are closer to the LED array. In view of the simulation experimental analyses of the present invention, it is believed that at least 30% of the stray light ratio can be reduced so as to enhance the LED display structure with better transparency and image quality.Type: GrantFiled: September 23, 2021Date of Patent: May 21, 2024Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITEDInventors: Che Wen Chiang, Tsung Yi Su, Po Lun Chen
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Patent number: 11991823Abstract: The present disclosure is relates to a conductive film and a manufacturing method thereof. The conductive film includes a base layer, a TPU complex layer, a conductive layer and a TPU surface layer. The TPU complex layer includes a TPU heat-resistant layer and a TPU melting layer. The TPU heat-resistant layer is disposed on the TPU melting layer, and the TPU melting layer is disposed on the base layer. The conductive layer includes a conductive circuit disposed on the TPU heat-resistant layer. The TPU surface layer is disposed on the conductive layer. Utilizing the TPU complex layer, the conductive layer does not contact directly with the base layer to avoid breaking the conductive line of the conductive layer when the base layer is pulled. Therefore, the lifetime of the conductive film can be increased.Type: GrantFiled: May 28, 2021Date of Patent: May 21, 2024Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chi-Chin Chiang, Wen-Hsin Tai, I-Ju Wu, Chi-Ho Tien
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Publication number: 20240162308Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.Type: ApplicationFiled: February 9, 2023Publication date: May 16, 2024Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
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Patent number: 11984486Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.Type: GrantFiled: January 23, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
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Patent number: 11975243Abstract: The present disclosure is relates to a TPU ball structure and a manufacturing method thereof. The TPU ball structure includes a ball bladder layer, a yarn layer and a surface layer. The ball bladder layer is made of TPU material. The yarn layer is made of TPU material, and the yarn layer is disposed to cover the ball bladder layer. The surface layer is made of TPU material, and the surface layer is disposed to cover the yarn layer. The above layers of the TPU ball structure are made of TPU material to satisfy a requirement for environmental protection, and are recyclable. There is no need to use adhesive to adhere the above layers of the TPU ball structure. Therefore, the peeling strength between the layers of the TPU ball structure can be increased so that the whole peeling strength of the TPU ball structure can be increased.Type: GrantFiled: April 22, 2021Date of Patent: May 7, 2024Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chi-Chin Chiang, Wen-Hsin Tai
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Patent number: 11971635Abstract: A U-shaped unit and a liquid crystal element with U-shaped coplanar electrode units provided by the invention are capable of increasing a horizontal electric field intensity in a power supply state, so that when the invention is applied to be used as a liquid crystal driving element, a required horizontal electric field intensity can be achieved with a lower driving voltage to reduce a required driving power when the liquid crystal element is used as a display screen, thereby achieving an effect of power saving.Type: GrantFiled: January 16, 2023Date of Patent: April 30, 2024Assignee: TUNGHAI UNIVERSITYInventors: Chia-Yi Huang, Wei-Fan Chiang, Yi-Hong Shih
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Publication number: 20240128217Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.Type: ApplicationFiled: January 20, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jung CHEN, Chen Chiang YU, Wei-An TSAO, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
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Publication number: 20240123463Abstract: An atomization module includes a main fixing member, an auxiliary fixing member, an atomization component and a piezoelectric component. The main fixing member includes a first bonding part, a second bonding part and a connecting part. The first bonding part has a first opening and a first bonding surface surrounding the first opening. The second bonding part is connected to the first bonding part, and the connecting part and the second bonding part surround the first bonding part. The auxiliary fixing member has a second opening and a second bonding surface surrounding the second opening. The piezoelectric component surrounds the first bonding part. The main fixing member has a first adhesive groove, which is jointly defined at least by the main fixing member, the auxiliary fixing member and the atomization component. The first adhesive is provided in the first adhesive groove.Type: ApplicationFiled: October 2, 2023Publication date: April 18, 2024Inventors: CHANG-HSIEH YAO, HSUN-WEI CHIANG, CHIA-CHIEN CHANG, HSIN-YI PAI, CHUN-CHIA JUAN
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Publication number: 20240120410Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.Type: ApplicationFiled: February 16, 2023Publication date: April 11, 2024Inventors: Yu-Tsu LEE, Yan-Ru CHEN, Chao-Yi CHANG, Kuang-Hao CHIANG
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Publication number: 20240113172Abstract: A semiconductor device includes a substrate, a channel layer, a gate structure, source/drain regions, and an insulating layer. The channel layer is disposed over the substrate. The gate structure is disposed over the channel layer. The source/drain regions are disposed over the substrate and disposed at two opposite sides of the channel layer. The insulating layer is disposed between the channel layer and the source/drain regions.Type: ApplicationFiled: March 5, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tse Hung, Meng-Zhan Li, Tzu-Chiang Chen, Chao-Ching Cheng, Iuliana Radu
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Patent number: D1026916Type: GrantFiled: January 5, 2022Date of Patent: May 14, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee