Patents by Inventor Yi-Chih Chang
Yi-Chih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140765Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.Type: ApplicationFiled: September 27, 2023Publication date: May 2, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Caung-Yu Liu
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Publication number: 20240147646Abstract: A portable data accessing device and more particularly the use of multi-port interfaces on a data accessing device disclosed. The multi-port data accessing device includes an inner body, one or a plurality of moving-caps, one or a plurality of grips, a pump-action and one or a plurality of locking/releasing mechanisms.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Yi-Ting Lin, Hsien-Chih Chang, Chang-Hsing Lin, Hao-Yin Lo, Ben Wei Chen
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Patent number: 11967622Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.Type: GrantFiled: September 3, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Patent number: 11961893Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.Type: GrantFiled: June 18, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
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Publication number: 20240120203Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.Type: ApplicationFiled: March 8, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
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Publication number: 20240116707Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Chung-Yu Liu
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Patent number: 11943936Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.Type: GrantFiled: August 12, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Der Chih, May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen Zhang Lin, Chrong Jung Lin, Ya-Chin King, Chieh Lee, Wang-Yi Lee
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Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
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Patent number: 11926266Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.Type: GrantFiled: August 26, 2022Date of Patent: March 12, 2024Assignee: PEGATRON CORPORATIONInventors: Shih-Wei Yeh, Chien-Chih Lin, Yi-Ming Chou, Chun-Chieh Chang
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Publication number: 20240079409Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyun-De WU, Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Peng WANG, Huan-Just LIN
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Patent number: 11851325Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.Type: GrantFiled: November 26, 2019Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei Chang, Ya-Jen Sheuh, Ren-Dou Lee, Yi-Chih Chang, Yi-Hsun Chiu, Yuan-Hsin Chi
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Publication number: 20220209554Abstract: A portable charging device is provided. The portable charging device includes a stylus module and a charging module. The stylus module includes a stylus body unit and a power supply unit. The power supply unit is arranged in the stylus body unit. The charging module includes a casing unit, a control unit, and a power storage unit. The casing unit includes an opening, a first accommodating space, and a second accommodating space. The opening is communicated with the first accommodating space, and the first accommodating space is adjacent to the second accommodating space. The control unit is arranged in the second accommodating space. The power storage unit is arranged in the second accommodating space and electrically connected to the control unit. The stylus body unit is detachably arranged in the first accommodating space, and the power supply unit is electrically connected to the control unit.Type: ApplicationFiled: March 25, 2021Publication date: June 30, 2022Inventors: HUNG-I WANG, YI-CHIH CHANG, CHIA-JUI YEH
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Patent number: 11023057Abstract: A stylus structure includes a stylus housing unit, a stylus cover unit, a control unit, and a barrier unit. The stylus housing unit has an accommodating space and an opening that are in spatial communication with each other. The stylus cover unit is detachably sleeved on the stylus housing unit. The control unit includes a processing component and a trigger component electrically connected to the processing component. The barrier unit in the accommodating space contacts the trigger component, and therefore the processing component is in a power OFF state. In another aspect, the stylus structure includes a stylus housing unit, a control unit, and a barrier unit. The control unit includes a processing component and electrically connects to a trigger component. The barrier unit in the stylus housing unit contacts the trigger component, and therefore the processing component is in a power OFF state.Type: GrantFiled: February 27, 2020Date of Patent: June 1, 2021Assignee: WALTOP INTERNATIONAL CORPORATIONInventors: Yi-Chih Chang, Ju-Ming Lin, Ying-Hwa Tang
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Publication number: 20210124436Abstract: A stylus structure includes a stylus housing unit, a stylus cover unit, a control unit, and a barrier unit. The stylus housing unit has an accommodating space and an opening that are in spatial communication with each other. The stylus cover unit is detachably sleeved on the stylus housing unit. The control unit includes a processing component and a trigger component electrically connected to the processing component. The barrier unit in the accommodating space contacts the trigger component, and therefore the processing component is in a power OFF state. In another aspect, the stylus structure includes a stylus housing unit, a control unit, and a barrier unit. The control unit includes a processing component and electrically connects to a trigger component. The barrier unit in the stylus housing unit contacts the trigger component, and therefore the processing component is in a power OFF state.Type: ApplicationFiled: February 27, 2020Publication date: April 29, 2021Inventors: YI-CHIH CHANG, JU-MING LIN, YING-HWA TANG
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Publication number: 20210117017Abstract: A stylus structure including a stylus housing unit, a magnetic attaching unit, and a cover unit is provided. The stylus housing unit includes a stylus body component and a touch control component disposed at an end of the stylus body component. A first magnetic member is disposed at another end of the stylus body component. The magnetic attaching unit is sleeved at another end of the stylus body component. The cover unit includes a cover body component and a supportive component, and a second magnetic member is disposed on the supportive component. The cover body component is detachably sleeved at another end of the stylus body component and magnetically attached to the magnetic attaching unit, and the second magnetic member and the first magnetic member are magnetically attached to each other.Type: ApplicationFiled: February 20, 2020Publication date: April 22, 2021Inventors: YI-CHIH CHANG, CHUNG-FUU MAO
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Patent number: 10895930Abstract: A message erasing device and a message erasing system, and the message erasing system includes a message erasing device and a message receiving device. The message erasing device includes a device body, a processing module, and an erasing module. The device body touches the message receiving device by a clearing unit and erases an actual message of the message receiving device, and the movable unit touches the processing module according to the clearing unit touching the message receiving device, so that the processing module generates an erasing signal to the message receiving device. The message receiving device provides a clear signal to an electronic device according to the erasing signal.Type: GrantFiled: August 7, 2019Date of Patent: January 19, 2021Assignee: WALTOP INTERNATIONAL CORPORATIONInventors: Yi-Chih Chang, Ying-Hwa Tang
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Publication number: 20200293124Abstract: A pressure triggered stylus structure including a stylus housing unit, a writing unit, an electrically conductive unit, a control unit, a first trigger unit, a second trigger unit, an elastic unit and a sensing unit is provided. When the writing unit is at an initial position and the electrically conductive unit is connected to the first trigger unit and the second trigger unit, the first trigger unit and the second trigger unit are in a connected state. On the other hand, when the writing unit is off the initial position and the electrically conductive unit is away from the first trigger unit and the second trigger unit, the first trigger unit and the second trigger unit are in a disconnected state, and the control unit detects a sensing state of the sensing unit according to the disconnected state.Type: ApplicationFiled: February 20, 2020Publication date: September 17, 2020Inventors: YI-CHIH CHANG, HUNG-I WANG, CHIH-HUNG HUANG
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Publication number: 20200172393Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Chien-Wei CHANG, Ya-Jen SHEUH, Ren-Dou LEE, Yi-Chih CHANG, Yi-Hsun CHIU, Yuan-Hsin CHI