Patents by Inventor Yi-Chih Wu

Yi-Chih Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967622
    Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Publication number: 20240120203
    Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240079409
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-De WU, Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Peng WANG, Huan-Just LIN
  • Publication number: 20240065765
    Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: Alvin Chao-Yu CHEN, Yi-Sheng CHAN, Chi-Pin HSU, Shang-Chih LIN, Chin-Ju WU, Jeng-Ywan JENG
  • Patent number: 11871510
    Abstract: A conductive pattern has been disclosed. The conductive pattern includes a pair of conductive traces. Each of the conductive traces comprises a linear portion and a terminal portion. The terminal portions are arranged adjacent to each other and comprises a pair of circular arc profile with a pair of complementary notches facing toward each other.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 9, 2024
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu, Feng-Hua Deng, Ming-Fang Chen
  • Patent number: 11596067
    Abstract: An apparatus having stacked circuit boards has been disclosed. The apparatus includes a main circuit board and a sub circuit board disposed over the main circuit board. A plurality of sub components disposed on a bottom face of the sub circuit board penetrates through main circuit board and extends towards a bottom face of the main circuit board. In this say, a compact apparatus is produced.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: February 28, 2023
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu
  • Publication number: 20220369474
    Abstract: A circuit board structure includes a rigid circuit board, a flexible circuit board, a plurality of conductive bumps, and a plurality of spacers. The rigid and flexible circuit boards are stacked one above the other. The conductive bumps are formed between the rigid and flexible circuit boards. The spacers are formed between the rigid and flexible circuit boards and spaced apart from the conductive bumps.
    Type: Application
    Filed: May 31, 2021
    Publication date: November 17, 2022
    Inventors: HOU-YUAN CHOU, XIAO-CHU JIN, SHI ZHANG, BO WU, ZHI-HONG XU, MEI-WEN KAO, YI-CHIH WU
  • Publication number: 20220232701
    Abstract: An apparatus having stacked circuit boards has been disclosed. The apparatus includes a main circuit board and a sub circuit board disposed over the main circuit board. A plurality of sub components disposed on a bottom face of the sub circuit board penetrates through main circuit board and extends towards a bottom face of the main circuit board. In this say, a compact apparatus is produced.
    Type: Application
    Filed: April 23, 2020
    Publication date: July 21, 2022
    Applicant: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: HOU-YUAN CHOU, YI-CHIH WU
  • Publication number: 20200323080
    Abstract: A circuit board optimized for a denser component population within a standard size of footprint includes a mother board and a plurality of sub-board layers stacked on and connected to the mother board. Each of the sub-board layers has a plurality of daughter boards. The sub-board layers are composed of a first sub-board layer and a second sub-board layer. The daughter boards of the first sub-board layer are arranged on a side of the mother board, and the daughter boards of the second sub-board layer are arranged on the daughter boards of the first sub-board layer.
    Type: Application
    Filed: May 7, 2019
    Publication date: October 8, 2020
    Inventors: HOU-YUAN CHOU, YI-CHIH WU
  • Patent number: 10785873
    Abstract: A circuit board optimized for a denser component population within a standard size of footprint includes a mother board and a plurality of sub-board layers stacked on and connected to the mother board. Each of the sub-board layers has a plurality of daughter boards. The sub-board layers are composed of a first sub-board layer and a second sub-board layer. The daughter boards of the first sub-board layer are arranged on a side of the mother board, and the daughter boards of the second sub-board layer are arranged on the daughter boards of the first sub-board layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 22, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., I, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu
  • Patent number: 10470308
    Abstract: A circuit board assembly comprising a printed circuit main board and a printed circuit sub-board, to avoid layout constraints, can support components on either board. The printed circuit main board includes first signal layer, and first and second through holes in the first signal layer. A first wire electrically couples a first electronic component and the first through hole. A second signal layer with third and fourth through holes is found on the printed circuit sub-board. The third through hole is electrically coupled to the first through hole, and the fourth through hole is electrically coupled to the second through hole.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 5, 2019
    Assignees: HONGFUJIN PRECISION INDUSTRY (WUHAN) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hou-Yuan Chou, Ming-Fang Chen, Yi-Chih Wu
  • Patent number: 10390430
    Abstract: A circuit board includes a board defining a holding slot and a connector. The connector includes a conductive column and a pad fixed to one end of the conductive column. The pad is received within the holding slot. The conductive column is fixed within the board. The pad is soldered to a connecting portion of an electrical component. The pad defines a first through hole receiving solder when the connecting portion of the electrical component is soldered to the pad.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 20, 2019
    Assignees: HONGFUJIN PRECISION INDUSTRY (WUHAN) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu