Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.

Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.

Abstract: A light-emitting device is provided. The light-emitting device generates a white light and includes at least one light-emitting diode. The at least one light-emitting diode generates a light beam with a broadband blue spectrum and includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well structure. The multiple quantum well structure is located between the first semiconductor layer and the second semiconductor layer, and includes well layers and barrier layers. The well layers include a first well layer, a second well layer and third well layers different in indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of the well layers that are closest to the first semiconductor layer are the third well layers, and the first well layer is closer to the second semiconductor layer than the first semiconductor layer.

Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Abstract: A valve for throttling gas flow from a semiconductor processing tool includes a valve body. A shaft extends through the valve body. The shaft defines an internal cavity and a first opening communicating with the internal cavity. A first deflector is positioned on the shaft proximate the first opening and directed at a first interface between the shaft and the valve body. A method for throttling gas flow from a semiconductor processing tool includes providing a gas in an internal cavity defined in a shaft of a valve and directing the gas through an opening defined in the shaft and communicating with the bore toward an interface between the shaft and a valve body of the valve supporting the shaft.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A connector connecting a main circuit board and a sub circuit board has two bases, two electrical contacting sets, two resilient bar sets and two mounting brackets. The bases are mounted on the main circuit board. The electrical contacting sets are mounted respectively in the bases and each electrical contacting set has multiple electrical contacting elements. The resilient bar sets are mounted respectively on the bases. The mounting brackets are mounted respectively on the bases and cover the electrical contacting sets and the resilient bar sets. Circuit-board-receiving channels are defined between the bases and the mounting brackets for receiving the sub circuit board such that combination of the main circuit board and the sub circuit board are parallel and flat.

Abstract: A connector connecting a main circuit board and a sub circuit board has two bases, two electrical contacting sets, two resilient bar sets and two mounting brackets. The bases are mounted on the main circuit board. The electrical contacting sets are mounted respectively in the bases and each electrical contacting set has multiple electrical contacting elements. The resilient bar sets are mounted respectively on the bases. The mounting brackets are mounted respectively on the bases and cover the electrical contacting sets and the resilient bar sets. Circuit-board-receiving channels are defined between the bases and the mounting brackets for receiving the sub circuit board such that combination of the main circuit board and the sub circuit board are parallel and flat.

Abstract: A connection base assembly for an IC testing apparatus has a base, a top cap and a conductive assembly. The base has a bottom board and an outer frame provided with multiple grooves. The grooves are defined in the top of and extend to the bottom of the outer frame to form multiple through holes in the bottom of the outer frame. The conductive assembly is mounted between the base and the top cap and has multiple conductive elements, multiple top resilient elements and multiple bottom resilient elements. The conductive elements are mounted respectively in the grooves in the outer frame of the base, and each conductive element has a contacting segment and a connecting segment. The top resilient elements and the bottom resilient elements are respectively mounted on and abut with the tops and the bottoms of the conductive elements.

Abstract: A connection base assembly for an IC testing apparatus has a base, a top cap and a conductive assembly. The base has a bottom board and an outer frame provided with multiple grooves. The grooves are defined in the top of and extend to the bottom of the outer frame to form multiple through holes in the bottom of the outer frame. The conductive assembly is mounted between the base and the top cap and has multiple conductive elements, multiple top resilient elements and multiple bottom resilient elements. The conductive elements are mounted respectively in the grooves in the outer frame of the base, and each conductive element has a contacting segment and a connecting segment. The top resilient elements and the bottom resilient elements are respectively mounted on and abut with the tops and the bottoms of the resilient elements.