Abstract: A method for assessing acute kidney injury of inpatient includes the following steps. An electronic medical record data of an inpatient is captured by a processor, and the electronic medical record data includes a baseline basic serum creatinine concentration data. A target serum creatinine concentration data and a minimum post-admission serum creatinine concentration data of the inpatient are captured by the processor. A dynamic-increasing value of serum creatinine concentration is calculated to obtain by the processor based on the target serum creatinine concentration data, the baseline basic serum creatinine concentration data and the minimum post-admission serum creatinine concentration data. The dynamic-increasing value of serum creatinine concentration is analyzed by the processor to assess whether the inpatient is an inpatient suffering the acute kidney injury or not.

Abstract: Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.

Abstract: The present disclosure relates to a method of identifying a genetic modifier of a nucleotide repeat disorder, comprising selecting from the subjects the late-onset subjects with higher nucleotide repeat load or the early-onset subjects with lower nucleotide repeat load and identifying one or more genetic modifiers delaying or promoting onset of a nucleotide repeat disorder. The present disclosure also relates to a method for treating or preventing a polyglutamine (polyQ) expansion disease in a subject in need of such treatment or prevention, comprising administering an effective amount of a PIAS1 variant or a recombinant nucleic acid molecule encoding the PIAS1 variant to the subject. The present disclosure also relates to a method for treating or preventing early symptoms onset of the polyglutamine expansion disease, a PIAS1 variant, comprising one or more sequence changes located in the C-terminal region of PIAS1 and a recombinant nucleic acid molecule encoding the PIAS1 variant as disclosed herein.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.

Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.

Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.

Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.