Abstract: A load balancing system and method is provided. The load balancing system includes a core network, CPEs (customer premise equipments), user equipments, and a load balancing equipment. The CPEs receive signals from the core network and connect to each other through a network topology. The user equipments are connected to the CPEs. The load balancing equipment is connected to one CPE, and the load balancing equipment confirms a throughput limit of each CPE and includes a data analysis module and a processing unit. The data analysis module receives network parameters between the CPEs and the user equipments, and calculates premise throughputs of the CPEs. The processing unit generates a route control table according to the premise throughputs. According to the route control table, the CPEs adjusts signal transmission between the CPEs and the user equipments to balance the premise throughputs of the CPEs.

Abstract: A data processing system is configured to sense a pressure readings of an air-mattress. If the pressure readings are below a target pressure value representing a desired pressure for the air-mattress, the data processing system can transmit, to an air-pump, first instructions to increase the air pressure of the air mattress and determine a replacement value representing the amount of air pumped into the air mattress by the air-pump. The data processing system can compare the replacement value to a slow-leak threshold and to a catastrophic-leak threshold. The data processing system can, responsive to a determination that the replacement value is greater than the slow-leak value and less than the catastrophic-leak value, transmit, to the air-pump, second instructions to increase the air pressure of the air mattress to replace air in the air mattress lost to a slow leak so as to maintain the desired pressure for the air-mattress.

Abstract: An electronic device includes a substrate, a signal line, a semiconductor, a first conductive portion and a second conductive portion. The signal line is disposed on the substrate. The semiconductor is disposed on the substrate and overlapped with the signal line. Wherein the semiconductor is electrically connected to the first conductive portion and the second conductive portion. Wherein in a top view, at least a portion of the signal line is disposed between the first conductive portion and the second conductive portion. Wherein the first conductive portion has a first curve edge, the second conductive portion has a second curve edge, and the first curve edge and the second curve edge are facing the at least a portion of the signal line and are convex toward the at least a portion of the signal line.

Abstract: Historical sleep metrics are accessed. Historical sensor data is accessed. Incidences of low quality sleep experienced by the user are identified. Particular environmental conditions that affected the user during the incidences of low quality sleep are identified. A corrective plan that specifies a change to an environmental control system to reduce the particular environmental conditions is created. The behavior of the environmental control system is modified such that the environmental control system reduces the particular environmental conditions when the user sleeps in the bed.

Abstract: A component processing apparatus including a carrying unit, a control unit and a processing module is provided. The carrying unit is adapted to carry an object to be processed. The control unit is signally connected to the carrying unit and defines a surface of the object to be processed as a plurality of processing areas. The processing module is controlled by the control unit. The processing module includes a transfer unit and a repair unit. The transfer unit is adapted to configure a plurality of components to each processing area according to a set sequence between the plurality of processing areas. The repair unit and the transfer unit process the object to be processed synchronously. Additionally, the repair unit removes a part of the components configured by the transfer unit in each processing area, or configures another component to a vacant position in each processing area.

Abstract: A microelectronic component transfer apparatus including a backplane carrier, a substrate carrier, a degluing laser source and a soldering laser source is provided. The backplane carrier is adapted to carry a backplane. The substrate carrier is adapted to carry a substrate. The substrate carrier and the backplane carrier are arranged opposite to each other. The degluing laser source is arranged on a side of the backplane carrier away from the substrate carrier. The degluing laser source is adapted to emit a degluing laser toward a direction of the substrate carrier. The soldering laser source is disposed on a side of the substrate carrier away from the backplane carrier. The soldering laser source is adapted to emit a soldering laser toward a direction of the backplane carrier. The microelectronic component transfer equipment is suitable for transferring a microelectronic component disposed on the substrate to the backplane.

Abstract: A micro light-emitting diode includes a first stacked layer, a second stacked layer, a third stacked layer, a bonding layer, at least one etch stop layer, and a plurality of electrodes. The second stacked layer is disposed between the first stacked layer and the third stacked layer. The first stacked layer includes a first active layer. The second stacked layer includes a second active layer. The third stacked layer includes a third active layer. The bonding layer is disposed between the second stacked layer and the third stacked layer. The at least one etch stop layer is at least disposed between the first active layer and the second active layer. The plurality of electrodes are respectively electrically connected with the first stacked layer, the second stacked layer, and the third stacked layer. At least one electrode of the plurality of electrodes contacts the etch stop layer.

Abstract: In one example, this disclosure describes an adjustable bed system that includes first and second adjustable foundations, at least one first motor to adjust the first adjustable foundation, at least one second motor to adjust the second adjustable foundation, a configurable device having a first state and a second state, and a central controller in communication with the device, the controller configured to receive an input representing one of the first state and the second state, the controller including a processor configured to control the at least one first motor and the at least one second motor based on the received input.

Abstract: A network connection control system and method is provided. The network connection control system includes user equipments, base stations, a server and a processing unit. Each base station has a connection range and is configured to connect the user equipment located within the connection range. Each user equipment transmits a network parameter between it and every base station through the base station connected therewith to the server. The server generates a QUBO matrix according to all the network parameters and outputs the QUBO matrix to the processing unit. The processing unit processes the QUBO matrix based on a quantum annealing algorithm to obtain an optimized connection configuration of the user equipments and base stations. The server receives the optimized connection configuration and controls the connection range of each base station accordingly for making an actual connection configuration of the user equipments and base stations identical with the optimized connection configuration.

Abstract: A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.

Abstract: Historical sleep metrics are accessed. Historical sensor data is accessed. Incidences of low quality sleep experienced by the user are identified. Particular environmental conditions that affected the user during the incidences of low quality sleep are identified. A corrective plan that specifies a change to an environmental control system to reduce the particular environmental conditions is created. The behavior of the environmental control system is modified such that the environmental control system reduces the particular environmental conditions when the user sleeps in the bed.

Abstract: A communication device includes a crystal oscillator, an auxiliary circuit, and a control circuit. The crystal oscillator provides a clock for operation of the communication device in a second mode. The auxiliary circuit includes an accumulator and a comparator. The accumulator counts a number according to an MDI (Medium Dependent Interface) signal. The comparator compares the number with a threshold. If the number is greater than or equal to the threshold, the comparator will output a wakeup signal. The control circuit switches from the second mode to a first mode in response to a control signal, and switches from the first mode to the second mode in response to the wakeup signal. In the first mode, the control circuit disables the crystal oscillator and enables the auxiliary circuit. In the second mode, the control circuit enables the crystal oscillator.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. Dimension of long side of the first display panel is D1, and the first display panel has first pixel resolution P1. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space d between the first display panel and the second display panel. Dimension of the long side of the second display panel is D2, and the second display panel has the second pixel resolution P2. Transmittance of the second display panel is T2. The multi-layer display module complies with T2>40%, P1?P2, and D ? 2 * T ? 2 ? d ? D ? 2 ? "\[LeftBracketingBar]" P ? 1 - P ? 2 ? "\[RightBracketingBar]" * P ? 2 .

Abstract: An Ethernet physical-layer transceiver includes a control circuit and a processing circuit. The control circuit sequentially employs a plurality of different phase combinations of a transmitter clock and a receiver clock for transmission and reception of data over a cable, and obtains a plurality of sets of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock, respectively. The processing circuit performs channel characteristic analysis according to the plurality of sets of samples provided by the control circuit.

Abstract: A sleep system comprises at least one mattress including a first sleep area for a first occupant, the first sleep area including a first section for a portion of a body of the first occupant, and a second sleep area adjacent to the first sleep area for a second occupant, the second sleep area including a second section for a portion of a body of the second occupant, an articulation system for articulating the first section and the second section, a first user controller configured to communicate with the articulation system in order to control articulation of the first section, and a second user controller configured to communicate with the articulation system in order to control articulation of the second section, wherein the first user controller is further configured to communicate with the articulation system in order to move the second section into a predetermined position.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space between the first display panel and the second display panel. Transmittance of the second display panel is T2, luminance of the first display panel is L1, and luminance of the second display panel is L2. The multi-layer display module complies with T ? 2 > 40 ? % and 0.8 ? L ? 1 L ? 2 * ( 1 - T ? 2 ) .

Abstract: A multi-layer display module includes a first display panel, and a second display panel. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space between the first display panel and the second display panel. Transmittance of the second display panel is T2, luminance of the first display panel is L1, and luminance of the second display panel is L2. The multi-layer display module complies with T ? 2 > 40 ? % and 0.8 ? L ? 1 L ? 2 * ( 1 - T ? 2 ) .

Abstract: A multi-layer display module includes a first display panel, and a second display panel. Dimension of long side of the first display panel is D1, and the first display panel has first pixel resolution P1. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space d between the first display panel and the second display panel. Dimension of the long side of the second display panel is D2, and the second display panel has the second pixel resolution P2. Transmittance of the second display panel is T2. The multi-layer display module complies with T2>40%, P1?P2, and D ? 2 * T ? 2 ? d ? D ? 2 ? "\[LeftBracketingBar]" P ? 1 - P ? 2 ? "\[RightBracketingBar]" * P ? 2 .

Abstract: An electronic device includes a substrate, a signal line, a semiconductor, a first conductive portion and a second conductive portion. The signal line is disposed on the substrate. The semiconductor is disposed on the substrate and overlapped with the signal line. Wherein the semiconductor is electrically connected to the first conductive portion and the second conductive portion. Wherein in a top view, at least a portion of the signal line is disposed between the first conductive portion and the second conductive portion. Wherein the first conductive portion has a first curve edge, the second conductive portion has a second curve edge, and the first curve edge and the second curve edge are facing the at least a portion of the signal line and are convex toward the at least a portion of the signal line.

Abstract: A thin film transistor substrate includes a substrate, a first conductive element and a semiconductor. The first conductive element is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The semiconductor is disposed on the substrate. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. In a top view, a virtual extending line disposes between the trace portion and the protrusive portion, the virtual extending line overlaps the second edge. At least a part of the semiconductor extends beyond the virtual extending line along a second direction vertical to the first direction.