Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes an upper surface; a plurality of exposed regions, formed in the semiconductor stack and exposing the upper surface; a lower protective layer, covering the exposed regions and the second semiconductor layer; a first reflective structure, formed on the second semiconductor layer and including a plurality of first openings on the second semiconductor layer; a second reflective structure, formed on the first reflective structure and electrically connected to the second semiconductor layer through the plurality of first openings; and an upper protective layer, formed on the second reflective structure; wherein the upper protective layer contacts and overlaps the lower protective layer on the exposed regions; wherein the first reflective structure and the

Abstract: A two-stage system and method for treating fluoride-containing wastewater are provided. The two-stage system includes a first concentration defluoridation section and a second concentration defluoridation section. In the first concentration defluoridation section, the first mixed wastewater containing high concentration of fluoride ions is mixed with calcium chloride and stirred in the second mixing tank to obtain the second mixed wastewater containing low-concentration fluoride ions; in the second concentration defluoridation section, the second mixed wastewater is mixed with an advanced defluoridation agent and stirred in the third mixing tank to form a third mixed wastewater; the third mixed wastewater is introduced into a flocculation tank from the third mixing tank; and polymer is added for flocculation and sedimentation, so as to discharge a sediment and a defluoridation wastewater, the fluoride ion of which is less than 15 ppm.

Abstract: A hotspot communication stabilization system includes a hotspot communication stabilizer. The hotspot communication stabilizer includes a connected device address search unit and a comparator. The connected device address search unit serves to obtain at least one connection address from a communication host device at regular or irregular intervals. The connection address is an address of a peripheral communication device connected to the communication host device and is stored in a connection address table. The comparator serves to determine whether there is a missing address in the connection address table at a current time by comparing two connection addresses of the peripheral communication device at two adjacent times. The missing address is sent to the communication host device and the communication host device re-establishes a hotspot signal connection to the missing address corresponded to a corresponding peripheral communication device.

Abstract: An advanced defluoridation agent and a method for removing fluoride ions in fluorine-containing wastewater are provided. The advanced defluoridation agent includes 40-70 wt % of polyaluminum sulfate, 0.3-30 wt % of hydroxyapatite and deionized water supplemented to 100 wt %. Using the advanced defluoridation agent of the present disclosure to treat fluoride-containing wastewater can achieve increased defluorination efficiency, reduced electrical conductivity, and reduced sludge content, and a better defluorination effect. The concentration of fluoride ions is lower than 15 ppm after using the advanced defluoridation agent of the present disclosure.

Abstract: Historical sleep metrics are accessed. Historical sensor data is accessed. Incidences of low quality sleep experienced by the user are identified. Particular environmental conditions that affected the user during the incidences of low quality sleep are identified. A corrective plan that specifies a change to an environmental control system to reduce the particular environmental conditions is created. The behavior of the environmental control system is modified such that the environmental control system reduces the particular environmental conditions when the user sleeps in the bed.

Abstract: A communication device includes a crystal oscillator, an auxiliary circuit, and a control circuit. The crystal oscillator provides a clock for operation of the communication device in a second mode. The auxiliary circuit includes an accumulator and a comparator. The accumulator counts a number according to an MDI (Medium Dependent Interface) signal. The comparator compares the number with a threshold. If the number is greater than or equal to the threshold, the comparator will output a wakeup signal. The control circuit switches from the second mode to a first mode in response to a control signal, and switches from the first mode to the second mode in response to the wakeup signal. In the first mode, the control circuit disables the crystal oscillator and enables the auxiliary circuit. In the second mode, the control circuit enables the crystal oscillator.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. Dimension of long side of the first display panel is D1, and the first display panel has first pixel resolution P1. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space d between the first display panel and the second display panel. Dimension of the long side of the second display panel is D2, and the second display panel has the second pixel resolution P2. Transmittance of the second display panel is T2. The multi-layer display module complies with T2>40%, P1?P2, and D ? 2 * T ? 2 ? d ? D ? 2 ? "\[LeftBracketingBar]" P ? 1 - P ? 2 ? "\[RightBracketingBar]" * P ? 2 .

Abstract: A temperature-sensitive and humidity-regulating fiber includes a polymer. The polymer includes a polyester main chain and at least one side chain, and the side chain is connected to the polyester main chain. The side chain is a structure shown in Formula (1): in which R is an alkylene group.

Abstract: An Ethernet physical-layer transceiver includes a control circuit and a processing circuit. The control circuit sequentially employs a plurality of different phase combinations of a transmitter clock and a receiver clock for transmission and reception of data over a cable, and obtains a plurality of sets of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock, respectively. The processing circuit performs channel characteristic analysis according to the plurality of sets of samples provided by the control circuit.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.

Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.

Abstract: A sleep system comprises at least one mattress including a first sleep area for a first occupant, the first sleep area including a first section for a portion of a body of the first occupant, and a second sleep area adjacent to the first sleep area for a second occupant, the second sleep area including a second section for a portion of a body of the second occupant, an articulation system for articulating the first section and the second section, a first user controller configured to communicate with the articulation system in order to control articulation of the first section, and a second user controller configured to communicate with the articulation system in order to control articulation of the second section, wherein the first user controller is further configured to communicate with the articulation system in order to move the second section into a predetermined position.

Abstract: A motor stator winding structure includes a stator core and slot-positions. The stator core includes an insertion side and an extension side. The hairpin wires are configured to be arranged into slot-positions of the phase slots of the same phases of the polar regions. A first phase winding includes first hairpin wires of the hairpin wires inserted from an entry phase slot-position of a first phase. A second phase winding includes second hairpin wires of the hairpin wires inserted from an entry phase slot-position of a second phase. A third phase winding includes third hairpin wires of the hairpin wires inserted from an entry phase slot-position of a third phase. The entry phase slot-position of the first phase, the entry phase slot-position of the second phase and the entry phase slot-position of the third phase are located in three different polar regions respectively.

Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.

Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: A package assembly includes a substrate, an electronic component and a cover. The electronic component and the cover are disposed on the substrate, wherein the electronic component is located within a chamber between the cover and the substrate. A cooling liquid may be filled in a heat dissipation space of the cover, so as to dissipate the heat generated by the electronic component. Furthermore, the cooling liquid may be filled in the chamber where the electronic component is located, so as to directly dissipate the heat generated by the electronic component.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space between the first display panel and the second display panel. Transmittance of the second display panel is T2, luminance of the first display panel is L1, and luminance of the second display panel is L2. The multi-layer display module complies with T ? 2 > 40 ? % and 0.8 ? L ? 1 L ? 2 * ( 1 - T ? 2 ) .