Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract: A foldable power supply device includes a first socket, a second socket, and a pivoting unit. The first socket has multiple sets of first plugging holes and first conductive plates. The second socket has multiple sets of second plugging holes and second conductive plates. The pivoting unit is located between the first socket and the second socket. The direction of the rotation shaft of the pivoting unit is not parallel to the plugging direction of the first plugging holes and the second plugging holes. Thereby, the foldable power supply device can be opened into a block type to lower its height and be used as a multi-hole type. Alternatively, the device can also be folded to become a vertical type so that one side of the device can align with the wall, and the plugs or the transformers can be plugged into the device in two face-to-face directions.

Abstract: A retractable extension socket includes an socket body, a fixing structure, a receiving structure, a conducting wire and a plug. The fixing structure and the receiving structure are disposed on the socket body. One end of the conducting wire is connected to the socket body. The plug is connected to the other end of the conducting wire. Thus, a retractable extension socket is formed. The retractable extension socket can be used as an extension socket. In addition, by winding the cable into the socket body and attaching the plug into the fixing structure, the retractable extension socket can be used as a single plug. Furthermore, the plug can be collected into the receiving structure in order that it can be carried around easily.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract: A mobile device with a releasable power storage device is provided. The mobile device comprises a cabinet, a power storage device detachably engaged with the cabinet, a latch disposed on the cabinet adjacent to a side wall thereof and capable of moving along the side, and an engaging portion engaged with the latch. The power storage device comprises a stopping portion and a guiding portion. The stopping portion and the engaging portion are alternatively disposed on one side of the body. When an external force is exerted on the engaging portion, the latch is moved to push the guiding portion of the power storage so as to eject the power storage device from the cabinet.

Abstract: The invention provides an improved process for preparing organic amine borane complex characterized in that it takes advantage of the slow reaction of potassium borohydride with water and the increased solubility in an ether/water mixed solvent containing minor amount of sodium hydroxide, adding slowly an organic amine to control the reaction rate and effectively control the generation of hydrogen gas in a manner to increase the yield and ensure the process safety.

Abstract: A semiconductor package, which is to attach an electric device, such as a die, thereon and electrically connect therewith, has a substrate with a conductor pattern thereon. The conductor pattern consists of a plurality of traces in a specific layout. The conductor pattern has conducting portions on which is provided with a conductor member respectively. The conductor members locate at positions above the conducting portion of the conductor pattern with a bottom surface thereof electrically connecting a top surface of the conducting portion. A solder mask is provided on the substrate sheltering the conductor pattern but exposing at least a top surface of the conductor member. Whereby, the conductor can electrically connect the electric device via the conductor members.

Abstract: Two methods for substantially improving the integrity of a TiN barrier layer are disclosed. The first method allows an atmospheric anneal in a conventional semiconductor furnace. The atmospheric anneal substantially seals the exposed TiN surface preventing subsequent metal layers from migrating through the barrier layer. The second method involves a reaction within a plasma reactor using a plasma gas. The plasma gas reacts with titanium within the TiN film to form a desired titanium compound. The gas is adsorbed onto the TiN grains at the grain boundaries within the TiN film thus filling the grain boundaries and thus substantially preventing subsequent metal layers from migrating though the TiN barrier layer. The second method allows the deposition of TiN, the plasma reaction, and subsequent metal depositions to take place on the same equipment using the same evacuation cycle.

Abstract: Methods of forming a semiconductor substrate and a device oriented substantially along a crystal direction other than a crystal direction that falls along a cleavage plane and the substrate and device formed by each method are disclosed. An ingot of monocrystalline material is formed and marked to denote a crystal direction other than a crystal direction that falls along a cleavage plane. The ingot is lapped to form a semiconductor substrate having a mark denoting a crystal direction other than a crystal direction that falls along a cleavage plane. A device is formed on the semiconductor substrate having a monocrystalline layer, such that a field oxide-active area edge or a gate electrode lies substantially along a crystal direction other than a crystal direction that falls along a cleavage plane. The present invention may be used on any device where dislocation defects, a lateral diffusion, or a lateral oxidation is to be minimized.

Abstract: A method of forming a device having an intermetal dielectric film which is formed and annealed to prevent a significant quantity of ambient moisture from being absorbed by the intermetal dielectric film prior to passivation layer deposition is disclosed. An intermetal dielectric layer is formed over a substrate having a interconnection layer. A second interconnect layer is formed over the IMD layer. The substrate with the intermetal dielectric is annealed anytime between IMD formation and passivation layer deposition to produce a film that does not absorb a significant quantity of ambient moisture, and therefore, longer queue times can be utilized between the anneal and subsequent processing. The present invention reduces the amount of water in the device which reduces hot electron induced device degradation.

Abstract: The present invention teaches a two-and-one-half-level resist process, wherein a first planarizing resist layer is applied, an anti-reflective coating (which need not be a photoresist itself) is applied, and then a top photoresist layer is applied. The top layer is patterned conventionally, at a wavelength which the anti-reflective coating absorbs, and a flood exposure (preferably in deep ultraviolet light) is then used to transfer this pattern to the bottom planarizing resist layer. Good patterning of non-planar surfaces despite topography is thus achieved, and pattern degradation due to spurious reflections (e.g., from an aluminum layer being patterned) is avoided.