Abstract: A fabricating method of an SOT MRAM structure includes forming an SOT MRAM. The SOT MRAM includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

Abstract: A truncated EGFR (tEGFR) cell surface molecule and its uses is provided herein. The tEGFR cell surface molecule includes an EGFR domain IV and does not include an EGFR domain III and may be used, inter alia, as an in vivo tracking marker for genetically modified human T cells. Furthermore, the tEGFR cell surface molecule has cellular depletion potential through mediated through specific anti-domain IV EGFR antibodies. Thus, the tEGFR cell surface molecules provided herein may, inter alia, be used as a non-immunogenic selection tool, tracking marker, a depletion tool or a suicide gene for genetically modified cells having therapeutic potential.

Abstract: Systems and methods provide for communicating with an interactive voice response system using a graphical user interface. An audio stream that includes a voice content is received. The user device transcribes the audio stream. The user device processes the text to identify one or more options included in the voice content of the audio stream. The one or more options are then displayed. The user device receives a selection from the user and transmits an indication of the user selection.

Abstract: A method of manufacturing a gallium nitride device with field plate structure, including forming a passivation layer covering a substrate and a gate, forming recesses in the passivation layer to define a source region and a drain region, forming a source and a drain on the passivation layer, forming a first ILD layer, a stop layer and a second ILD layer sequentially on the source, the drain and the passivation layer, patterning the first ILD layer, the stop layer and the second ILD layer to form dual-damascene recesses, and filling metal in the dual-damascene recesses to form dual-damascene interconnects connecting respectively with the source and the drain.

Abstract: A tab pull is adapted to be installed on the slider, and includes: a gripping portion, which is configured in a sheet shape; a slider connection portion, which extends outward from a front end of the gripping portion and is adapted to pass through a tab pull installation portion of the slider; an engaged portion, which is located on one of the side surfaces of the gripping portion in a width direction; and an engagement portion, which is extending outward from an end portion of the slider connection portion. The engagement portion is fitted into the engaged portion along the side surface of the gripping portion, so that the slider connection portion is closed to form an annular shape.

Abstract: A semiconductor structure with an MIM capacitor includes a first transistor. The first transistor includes a source and a drain. An interlayer dielectric layer covers the first transistor. A source plug penetrates the interlayer dielectric layer and contacts the source. A drain plug penetrates the interlayer dielectric layer and contacts the drain. A metal interlayer dielectric layer covers the interlayer dielectric layer. An MIM capacitor is disposed in the interlayer dielectric layer and the metal interlayer dielectric layer.

Abstract: Supramolecular nanostructures having spatially distinct features and methods for the preparation of such nanostructures are disclosed. The supramolecular nanostructures are composed of planar, or linear small molecules associated with each other through non-covalent interactions including, but not limited to, metal-metal interactions, ?-? interactions, hydrogen bonding interactions, solvophobic-solvophobic interactions, or a combination thereof, and polymer components stabilized by non-covalent interactions. These supramolecular nanostructure materials can exhibit a wide variety of functional properties due to the two chemically diverse components, in which a great flexibility and a large variety of choices are available, enabling options to control the supramolecular nanostructure's luminescence properties and compositions.

Abstract: A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.

Abstract: A semiconductor device includes a substrate, magnetic tunnel junction (MTJ) structures, and a write structure. The MTJ structures are disposed above the substrate. The write structure is disposed on and connected with the MTJ structures. The write structure includes spin-orbit torque (SOT) patterns and an electrically conductive layer. The SOT patterns are separated from one another, and each of the SOT patterns is disposed on and connected with one of the MTJ structures. The conductive layer covers the SOT patterns. The electrically conductive layer is partly disposed above the SOT patterns in a vertical direction and partly disposed between the SOT patterns in a first horizontal direction.

Abstract: A method for calibrating sensed force of a touch pad module is provided. The touch pad module includes a touch pad and force sensing elements disposed therebeneath. The method includes: obtaining a force reference table obtained before the touch pad module is assembled with an electronic device, the force reference table including a first data, which includes a first point of the touch pad and first force reference values corresponding to the first point and respectively corresponding to the force sensing elements; placing a calibration block on the first point after the touch pad module is assembled with the electronic device, so the force sensing elements respectively obtain first force test values corresponding to the first point; calculating first compensation ratios according to the first force reference values and the first force test values; and inputting the first compensation ratios into the force reference table.

Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A device comprising a die substrate; a plurality of interconnects located over the die substrate, wherein the plurality of interconnects comprise a first plurality of interconnects comprising a first plurality of via interconnects, wherein the first plurality of interconnects are configured as a first inductor; and a second plurality of interconnects comprising a second plurality of via interconnects, wherein the second plurality of interconnects are configured as a second inductor; wherein the first inductor and the second inductor are intertwined, at least one magnetic layer that surrounds at least part of the first plurality of via interconnects and at least part of the second plurality of via interconnects; and at least one dielectric layer located over the die substrate.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area.

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.