Patents by Inventor Yi-Chiu Tsai

Yi-Chiu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8995100
    Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 31, 2015
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
  • Publication number: 20130249046
    Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen