Patents by Inventor Yi Chou

Yi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151372
    Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250113539
    Abstract: A method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250085570
    Abstract: A functional patch for use with a contact lens includes an attaching layer and a functional patterned layer. The contact lens and the attaching layer are made of different hydrophilic materials to present two net-like structures respectively contain a plurality of first pores and second pores, and the second pores have pore size smaller than that of the first pores. The attaching layer is adsorbable to and detachable from the contact lens. A part of the functional patterned layer permeates into the second pores and the remaining part of the functional patterned layer is cured on the surface of the attaching layer. The attaching layer has closely arranged molecular chain blocks to form net-like structure having relatively small pore size. Therefore, only a limited amount of the material molecules of the functional patterned layer is permeated into the second pores, allowing the functional patterned layer to have a smooth surface.
    Type: Application
    Filed: July 9, 2024
    Publication date: March 13, 2025
    Applicant: OPENVISION CORPORATION
    Inventors: Ming-Yi CHOU, Ta-Jen HSING, Sung-Yuan CHIANG, Takahiro TAKAHASHI
  • Publication number: 20250087482
    Abstract: A device includes gate spacers, a gate dielectric layer, and one or more gate metals. The gate spacers are over a substrate. The gate dielectric layer is between the gate spacers. The gate dielectric layer includes a horizontal portion extending parallel to a top surface of the substrate, and vertical portions extending upwards from the horizontal portion. A first one of the vertical portions has a thickness less than a thickness of the horizontal portion.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Publication number: 20250072052
    Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 27, 2025
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250060398
    Abstract: A capacitance measurement circuit includes a charge to voltage converter (CVC) that includes at least one first variable capacitor, an excitation signal generation circuit, a differential amplifier, a first switch circuit, and at least one second variable capacitor, wherein a parasitic capacitance from a sensing capacitance sensed by a capacitance sensor is reduced by the at least one first variable capacitor. The excitation signal generation circuit is arranged to generate and connect a first excitation signal to the capacitance sensor, and generate and connect a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are out-of-phase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal. The inverting input terminal of the differential amplifier is arranged to receive the sensing capacitance from the capacitance sensor.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Applicant: Elite Semiconductor Microelectronics Technology Inc.
    Inventor: Yi-Chou Huang
  • Patent number: 12212708
    Abstract: A ringing suppression circuit applicable to a transmitter module in a controller area network is provided, which includes a CANH driver circuit, a CANL driver circuit, a first operable circuit transmitting a CAN high signal, a second operable circuit transmitting a CAN low signal, and a termination component connected between the first operable circuit and the second operable circuit. By sequentially turning on a first, second, and third transistor of the CANH driver circuit and sequentially turning on a fourth, fifth, and sixth transistor of the CANL driver circuit, conventional ringing phenomenon is effectively suppressed. A plurality of transistors may also be configured for implementing the CANH driver circuit or the CANL driver circuit for further reducing a glitch. The transmitter module employing the proposed ringing suppression circuit is able to pull the bus to a recessive state and meanwhile suppress the ringing and improve the maximum data rate.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: January 28, 2025
    Assignee: AMAZING MICROELECTRONIC CORP.
    Inventor: Ting-Yi Chou
  • Patent number: 12191144
    Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Patent number: 12179626
    Abstract: A structure for holding a battery on an automated guided vehicle (AGV) so as to allow easy and convenient battery replacement includes two fixed supports and a bracket. The bracket is connected between the two supports and each support defines a vertical groove and two horizontal grooves. Two sliders at the ends of the bracket are insertable into either horizontal groove. The two sliders can move down along the vertical groove together until the bracket makes contact with the battery and holds it in place. The two sliders can move up along the vertical groove and sideways into the horizontal grooves, thereby unlatching and releasing the battery for rapid replacement. An AGV using the structure is also disclosed.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: December 31, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hun-Yi Chou, Chih-Cheng Lee, Yu-Sheng Chang, Yu-Cheng Zhang, Hsiu-Fu Li, Chang-Ju Hsieh, Tsung-Hsin Wu, Chiung-Hsiang Wu, Chen Chao, Chen-Ting Kao, Chi-Cheng Wen, Sheng-Li Yen
  • Publication number: 20240419748
    Abstract: Systems and methods are provided for implementing adaptable embedded search engine functionality. In an aspect, a shared SERP system receives a user search query from a first search utility among a plurality of search utilities, which is associated with corresponding apps that are different from each other. A router of the shared SERP system provides the user search query and location information to a first query builder among one or more query builders of the shared SERP system. The first query builder constructs a query request corresponding to the user search query, based on the provided user search query and location information. A first query executor among one or more query executors of the shared SERP system executes the query request to produce search results. A component renderer of the shared SERP system renders one or more UX components within the first SERP, based on the search results.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Alicia Oliva COLL, Jose Miguel RIVERA DAVALOS, Qiwen GUO, Raghu R. NADIMINTI, Andreas Allern BROSE, Bjørnstein LILLEBY, Steffen Viken VALVÅG, Gordon Bradford JENSEN, Luke ROBERTS, Soujanya SRIVALLI, Jon MELING, Sheng Yi CHOU, Tracey SAUR, Tudor POPA, Mikael SVENSON, Ajla BADZA
  • Publication number: 20240314959
    Abstract: A retention mechanism is provided for retaining graphics add-in cards in an information handling system. The retention mechanism includes a mount and a retention bracket. The mount is affixed to the information handling system and includes mounting locations. The retention bracket is configured to be affixed to a particular one of the mounting locations and includes an adjustable filler device. The filler device is configured to secure a first graphics add-in card having a first width with the filler device located in a first position, and to secure a second graphics add-in card having a second width that is wider than the first width with the filler device located in a second position.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Inventors: HsienWei Chen, Yu-Tai Sheng, Pei-Yi Chou, Che-Ling Huang
  • Patent number: 12092672
    Abstract: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: September 17, 2024
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventor: Yi-Chou Huang
  • Patent number: 12064754
    Abstract: A titanium catalyst and a synthesizing method of polyester resins are provided in the present disclosure. The titanium catalyst has a chemical structure represented by Formula (I), Formula (II) or Formula (III). The symbols shown in the Formula (I), the Formula (II) or the Formula (III) are defined in the description. The synthesizing method of polyester resins includes providing the titanium catalyst, performing a feeding step, performing a heating and pressurizing step and performing a heating and vacuuming step. The titanium catalyst and a heat stabilizer are added into an autoclave before the feeding step or before the heating and vacuuming step.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: August 20, 2024
    Assignees: NATIONAL TSING HUA UNIVERSITY, CHANG CHUN PLASTICS CO., LTD., CHANG CHUN PETROCHEMICAL CO., LTD., DAIREN CHEMICAL CORP.
    Inventors: Yi-Chou Tsai, John Di Yi Ou, Chuan-Sheng Huang, Yung-Sheng Lin
  • Publication number: 20240240306
    Abstract: A physical vapor deposition (PVD) system includes: a pedestal configured to accommodate a semiconductor wafer; a cover plate above the pedestal configured to hold a target; and a collimator disposed above the pedestal and below the cover plate. The collimator has an upper surface and a lower surface. The lower surface is flat, and the upper surface is non-flat. A first thickness, in a vertical direction, of the collimator at a central portion is smaller than a second thickness, in the vertical direction, of the collimator at a peripheral portion.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 18, 2024
    Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang
  • Patent number: 12033850
    Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: July 9, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Patent number: 12026096
    Abstract: Disclosed are an on-demand shared data caching method, a computer program, and a computer readable medium applicable for distributed deep learning computing. The method includes a step of dynamically building a distributed shared memory cache space, in which a distributed shared memory deployment and data file access management module is added to a deep learning framework to build the distributed shared memory cache space by a memory set of a multiple of computing nodes of a cluster computer; and a distributed deep learning computing step, in which the computing node overrides a Dataset API of the deep learning framework to execute the distributed deep learning computing. When reading a data file, if the data file exists in the distributed shared memory cache space, then it will be accessed directly, or else it will be obtained from an original specified directory location and stored in the distributed shared memory cache space.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: July 2, 2024
    Assignee: National Applied Research Laboratories
    Inventors: Yu-Bin Fang, Shuen-Tai Wang, Chau-Yi Chou
  • Publication number: 20240187533
    Abstract: A ringing suppression circuit applicable to a transmitter module in a controller area network is provided, which includes a CANH driver circuit, a CANL driver circuit, a first operable circuit transmitting a CAN high signal, a second operable circuit transmitting a CAN low signal, and a termination component connected between the first operable circuit and the second operable circuit. By sequentially turning on a first, second, and third transistor of the CANH driver circuit and sequentially turning on a fourth, fifth, and sixth transistor of the CANL driver circuit, conventional ringing phenomenon is effectively suppressed. A plurality of transistors may also be configured for implementing the CANH driver circuit or the CANL driver circuit for further reducing a glitch. The transmitter module employing the proposed ringing suppression circuit is able to pull the bus to a recessive state and meanwhile suppress the ringing and improve the maximum data rate.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Applicant: AMAZING MICROELECTRONIC CORP.
    Inventor: TING-YI CHOU
  • Publication number: 20240133934
    Abstract: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 25, 2024
    Applicant: Elite Semiconductor Microelectronics Technology Inc.
    Inventor: Yi-Chou Huang
  • Patent number: 11952656
    Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang
  • Patent number: D1072167
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 22, 2025
    Assignee: LAN SHAN ENTERPRISE CO., LTD.
    Inventor: Yi-Chou Lin