Patents by Inventor Yi Chou Lai

Yi Chou Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing substrate warpage in semiconductor processing
    Patent number: 8691706
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu
  • Reducing Substrate Warpage in Semiconductor Processing
    Publication number: 20130183831
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu