Patents by Inventor Yi-Chuan Ding

Yi-Chuan Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190244907
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Chia Ching CHEN, Yi Chuan DING
  • Publication number: 20180359853
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
  • Patent number: 9978705
    Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: May 22, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia-Ching Chen, Yi-Chuan Ding
  • Patent number: 9960121
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Publication number: 20160336287
    Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
    Type: Application
    Filed: July 28, 2016
    Publication date: November 17, 2016
    Inventors: Guo-Cheng LIAO, Chia-Ching CHEN, Yi-Chuan DING
  • Publication number: 20160315052
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Patent number: 9437565
    Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 6, 2016
    Assignee: ADVANCED SEMINCONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia-Ching Chen, Yi-Chuan Ding
  • Patent number: 9406552
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 2, 2016
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Publication number: 20160190079
    Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 30, 2016
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng LIAO, Chia-Ching CHEN, Yi-Chuan DING
  • Patent number: 9349611
    Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 24, 2016
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Ching Chen, Yi-Chuan Ding
  • Patent number: 9219048
    Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: December 22, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yun-Hsiang Tien, Yi-Chuan Ding
  • Patent number: 9117697
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 25, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che Lee, Yuan-Chang Su, Wen-Chi Cheng, Guo-Cheng Liao, Yi-Chuan Ding
  • Publication number: 20140367837
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Chun-Che LEE, Yuan-Chang SU, Wen-Chi CHENG, Guo-Cheng LIAO, Yi-Chuan DING
  • Publication number: 20140367852
    Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 18, 2014
    Inventors: Yun-Hsiang TIEN, Yi-Chuan DING
  • Publication number: 20140175663
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Patent number: 8624374
    Abstract: An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: January 7, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi-Chuan Ding, Chia-Ching Chen
  • Publication number: 20130171774
    Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Inventors: Chia-Ching Chen, Yi-Chuan Ding
  • Patent number: 8405213
    Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: March 26, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Ching Chen, Yi-Chuan Ding
  • Patent number: 8278746
    Abstract: Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: October 2, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi-Chuan Ding, Chia-Ching Chen
  • Publication number: 20110241193
    Abstract: An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 6, 2011
    Inventors: Yi-Chuan Ding, Chia-Ching Chen