Patents by Inventor Yi-Chuan Ding

Yi-Chuan Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956897
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 9, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Ze Lin, Chia Ching Chen, Yi Chuan Ding
  • Publication number: 20230402738
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 14, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Patent number: 11721884
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Publication number: 20220361326
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
  • Patent number: 11399429
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Ze Lin, Chia Ching Chen, Yi Chuan Ding
  • Patent number: 11362049
    Abstract: A semiconductor device package includes a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first supporting structure disposed on the first surface of the substrate and a second supporting structure disposed on the first surface of the substrate. The first supporting structure has a first surface spaced apart from the first surface of the substrate by a first distance. The second supporting structure has a first surface spaced apart from the first surface of the substrate by a second distance. The second distance is different from the first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the substrate. The first antenna is supported by the first surface of the first supporting structure and the first surface of the second supporting structure.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: June 14, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Patent number: 11296001
    Abstract: A package substrate includes a first dielectric layer, a first patterned conductive layer and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks of the first set of alignment marks and the first edge are different from each other.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Patent number: 11107777
    Abstract: A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 31, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Publication number: 20210226317
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20210202410
    Abstract: A semiconductor device package includes a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first supporting structure disposed on the first surface of the substrate and a second supporting structure disposed on the first surface of the substrate. The first supporting structure has a first surface spaced apart from the first surface of the substrate by a first distance. The second supporting structure has a first surface spaced apart from the first surface of the substrate by a second distance. The second distance is different from the first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the substrate. The first antenna is supported by the first surface of the first supporting structure and the first surface of the second supporting structure.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Patent number: 10971798
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 6, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Patent number: 10847470
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia Ching Chen, Yi Chuan Ding
  • Publication number: 20200296827
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
  • Patent number: 10687419
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 16, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Ze Lin, Chia Ching Chen, Yi Chuan Ding
  • Publication number: 20200127366
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure.
    Type: Application
    Filed: April 4, 2019
    Publication date: April 23, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20200126881
    Abstract: A package substrate includes a first dielectric layer, a first patterned conductive layer and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks of the first set of alignment marks and the first edge are different from each other.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 23, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20190363056
    Abstract: A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20190244907
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Chia Ching CHEN, Yi Chuan DING
  • Publication number: 20180359853
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
  • Patent number: 9978705
    Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: May 22, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia-Ching Chen, Yi-Chuan Ding