Patents by Inventor Yi-Chuan Yang

Yi-Chuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070136572
    Abstract: An encrypting system to protect digital data and a method thereof are disclosed. During dispatching files to receivers, a compiler is used to add a file key on out-going file to form the first encrypted electronic text and to retrieve file abstract, and then the first encrypted electronic text is encrypted again with a public key to form the second encrypted electronic text which is stored into a database of a server. The file abstract as well as the file key is also encrypted by the public key before being sent to the receivers. The receivers then decrypt the encrypted file by the public key to obtain the original file abstract with which the receivers get the download permission from the server to download the second encrypted electronic text. The receivers then download and decrypt the second encrypted electronic text by the public key into the first encrypted electronic text which is then opened by the compiler by means of the file key to meet the purpose of protecting digital data.
    Type: Application
    Filed: May 4, 2006
    Publication date: June 14, 2007
    Inventors: Yen-Fu Chen, Shiuan-Sz Wang, Yi-Chuan Yang, Kuo-Tien Lee
  • Patent number: 7015112
    Abstract: Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS as a source to deposit an oxide layer on the bottom and sidewall of the trench structure and the semiconductor substrate; and removing the oxide layer on the sidewall of the trench structure substantially completely and the oxide layer on the bottom of the trench structure partially to define the remained oxide layer as the bottom oxide layer.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: March 21, 2006
    Assignee: Mosel Vitelic, Inc.
    Inventors: Ta-Chung Wu, Yi-Chuan Yang, Shih-Chi Lai, Yew-Jung Chang
  • Patent number: 6974749
    Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: December 13, 2005
    Assignee: Mosel Vitelic, Inc.
    Inventors: Shih-Chi Lai, Yifu Chung, Yi-Chuan Yang, Jen-Chieh Chang, Jason Chien-Sung Chu, Chun-De Lin
  • Publication number: 20040203217
    Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.
    Type: Application
    Filed: October 1, 2003
    Publication date: October 14, 2004
    Applicant: MOSEL VITELIC, INC.
    Inventors: Shih-Chi Lai, Yifu Chung, Yi-Chuan Yang, Jen-Chieh Chang, Jason Chien-Sung Chu, Chun-De Lin
  • Publication number: 20040152271
    Abstract: Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS as a source to deposit an oxide layer on the bottom and sidewall of the trench structure and the semiconductor substrate; and removing the oxide layer on the sidewall of the trench structure substantially completely and the oxide layer on the bottom of the trench structure partially to define the remained oxide layer as the bottom oxide layer.
    Type: Application
    Filed: September 22, 2003
    Publication date: August 5, 2004
    Applicant: MOSEL VITELIC, INC.
    Inventors: Ta-Chung Wu, Yi-Chuan Yang, Shih-Chi Lai, Yew-Jung Chang
  • Publication number: 20020146909
    Abstract: A method of smoothing an inter-metal dielectric layer in a semiconductor device for reducing formation of voids. The method comprises the steps of: providing a semiconductor substrate with metal lines formed thereon; forming a first dielectric layer on the surface of the semiconductor substrate, covering the metal lines; forming a pre-planarization layer, with high fluidity and good gap-fill capacity, on the first dielectric layer; forming a spin-on layer on the pre-planarization layer; etching back the spin-on layer until exposing the pre-planarization layer; and forming a second dielectric layer on the pre-planarization layer and the spin-on layer. Furthermore, an IMD structure fabricated via the method is also disclosed.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 10, 2002
    Inventors: Yi-chuan Yang, Jason C.S. Chu
  • Patent number: 6326320
    Abstract: A method for forming oxide layer on conductor plug of trench structure is proposed. The invention includes following essential steps: First, provide a substrate where a trench locates inside the substrate, herein the trench is partly filled by a conductor plug. Second, forms a plasma enhanced tetraethyl-orthosilicate layer on the substrate, herein the plasma enhanced tetraethyl-orthosilicate layer also fills the trench and covers the conductor plug. Finally, removes the plasma enhanced tetraethyl-orthosilicate layer until the substrate is not covered by the plasma enhanced tetraethyl-orthosilicate layer, herein the conductor plug still is covered by the plasma enhanced tetraethyl-orthosilicate layer. Additional, advantages of application of plasma enhanced tetraethyl-orthosilicate layer comprise compacted structure and high deposit rate.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: December 4, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Yi-Chuan Yang, Jason Chien-Song Chu, Mike Wen-Jeh Su
  • Patent number: 6261893
    Abstract: The present invention relates to a method for forming a magnetic layer of magnetic random access memory. In short, the method comprises following steps: providing a substrate; forming metal structures on substrate; forming a stop layer on substrate and mostly conformally covers metal structures; forming a buffer layer which mostly conformally covers stop layer; forming a dielectric layer on buffer layer where thickness of dielectric layer is larger than height of metal structures; planarizing the surface of said dielectric layer; and forming a magnetic layer on dielectric layer. Moreover, some essential key-points of the method are dielectric layer is more sensitive to said stop layer than buffer layer and gap fill ability of dielectric layer is better than gap fill ability of buffer layer.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: July 17, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Yen-Jung Chang, Yi-Chuan Yang, Jun-Jei Huang, Mo-Chung Tseng
  • Patent number: 6090725
    Abstract: A method for preventing bubble defects in borophosphosilicate glass (BPSG) film is provided. A wafer for depositing borophosphosilicate glass (BPSG) film is loaded in deposition chamber. After the wafer is properly positioned, the wafer is heated to a predetermined temperature. A process gas is introduced from the gas distribution system to the deposition chamber. A selected pressure of the deposition chamber is set and maintained throughout deposition process. After deposition of the BPSG film, the wafer is loaded out the chamber. Subsequently, helium gas is introduced to purge the liquid injection valve and delivery path. After pumping out the purge gas, the another wafer is then loaded in the chamber for depositing BPSG film.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: July 18, 2000
    Assignee: Mosel Vitelic Inc.
    Inventors: Yi-Chuan Yang, Ching-Shun Lin, Mike W. J Sue, Chih-Ta Wu