Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Abstract: In some aspects of the present disclosure, a power detection system is disclosed. In some aspects, the power detection system includes a constant-transconductance (gm) reference generator circuit receiving a power supply voltage. In some embodiments, the constant-gm reference generator circuit includes a first current mirror to provide a first reference voltage and a second current mirror to provide a second reference voltage. In some embodiments, the constant-gm reference generator circuit includes a power detection circuit coupled to the first current mirror to receive the first reference voltage. In some embodiments, the power detection circuit is coupled to the second current mirror to receive the second reference voltage. In some embodiments, the power detection is operated to receive the power supply voltage. In some embodiments, the power detection circuit is operated to provide an output voltage having one of two logic states at least based on the second reference voltage and the power supply voltage.

Abstract: A transparent display panel with a light-transmitting substrate, a plurality of top-emitting micro light emitting diodes, a plurality of bottom-emitting micro light emitting diodes, and a light shielding layer. The light transmissive substrate has a surface. These top-emitting micro light emitting diodes and these bottom-emitting micro light emitting diodes are disposed on the surface of the light transmissive substrate. The bottom-emitting micro light emitting diodes has an epitaxial structure and a light shielding member, the epitaxial structure has a pair of upper and lower surfaces on the opposite sides, the lower surface faces toward the light transmissive substrate, and the light shielding member is disposed on the upper surface to shield the light emitted by the bottom-emitting micro light emitting diodes towards the upper surface.

Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Abstract: A micro LED display device includes a substrate, micro LED units and a transparent insulation layer. The substrate includes conductive pads and conductive connecting portions. The conductive pads are disposed on the substrate. Each of the micro LED units includes a semiconductor epitaxial structure and electrodes. The electrodes are disposed on the semiconductor epitaxial structure, and each of the electrodes is connected to one of the conductive connecting portions adjacent to each other. The transparent insulation layer is disposed on the substrate and covers the conductive pads, the conductive connecting portions and the micro LED units, and the transparent insulation layer is filled between the electrodes of each of the micro LED units. The transparent insulation layer relative to a surface on each of the semiconductor epitaxial structures is of a first thickness and a second thickness, and the first thickness is different from the second thickness.

Abstract: A micro-electronic element transfer apparatus including a first conveyer portion, a second conveyer portion, and a light source device is provided. The first conveyer portion is configured to output a plurality of micro-electronic elements. The second conveyer portion includes a first rolling component and a substrate. The substrate is disposed on the first rolling component and is moved through rolling of the first rolling component. A plurality of bumps are disposed on the substrate. The light source device is configured to irradiate the bumps for heating, and the bumps generate a phase transition. When the micro-electronic elements are outputted from the first conveyer portion, a connection force between the micro-electronic elements and the first conveyer portion is less than a connection force between the micro-electronic elements and the bumps. The micro-electronic elements are respectively bonded to the bumps. A micro-electronic element transfer method is also provided.

Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.

Abstract: A micro LED display device includes a micro light emitting unit, a conductive structure and a substrate. The micro light emitting unit includes a plurality of micro light emitting elements, and each of the micro light emitting elements includes a semiconductor structure and an electrode structure. The semiconductor structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The electrode structure includes a first type electrode and a second type electrode. The conductive structure includes a first type conductive layer and a second type conductive layer. The first type conductive layer is electrically connected to the first type electrode, and the second type conductive layer is electrically connected to the second type electrode. The micro light emitting unit is disposed on the substrate, and the electrode structure is disposed toward the substrate and includes a gap therebetween.

Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Abstract: A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a plurality of memory cells, a first reference cell connected to a first subset of the plurality of memory cells via a first common source line, and a second reference cell connected to a second subset of the plurality of memory storage cells via a second common source line. The semiconductor device also includes a sense amplifier configured to, when reading from a first memory cell of the first subset, receive an output from the second reference cell and an output from the first memory cell.

Abstract: A micro semiconductor structure includes a substrate, a dissociative layer, a protective layer and a micro semiconductor. The dissociative layer is located on one side of the substrate. The protective layer is located on at least one side of the substrate. The micro semiconductor is located on the side of the substrate. The transmittance of the protective layer for a light source with wavelength smaller than 360 nm is less than 20%.

Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.

Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.