Abstract: Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.

Abstract: A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.

Abstract: A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor substrate, a protective layer formed on the semiconductor substrate, and a polysilicon layer formed on the protective layer; and removing the polysilicon layer. The wafer and the reclaiming method of the wafer can prevent the substrate of the wafer from being destroyed during the reclaiming process and increase the reclaiming rate of the wafer.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a gate electrode; a gate insulating layer formed on the gate electrode; a polysilicon layer formed on the gate insulating layer and including a pair of ohmic contact areas doped with conductive impurity; source and drain electrodes formed on the ohmic contact areas at least in part; a passivation layer formed on the source and the drain electrodes and having a contact hole exposing the drain electrode at least in part; and a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a gate electrode; a gate insulating layer formed on the gate electrode; a polysilicon layer formed on the gate insulating layer and including a pair of ohmic contact areas doped with conductive impurity; source and drain electrodes formed on the ohmic contact areas at least in part; a passivation layer formed on the source and the drain electrodes and having a contact hole exposing the drain electrode at least in part; and a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.