Patents by Inventor Yi-Da Chen
Yi-Da Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 10374310Abstract: A tunable antenna device includes a substrate, a switch, a control circuit, an antenna and a frequency adjustment portion. The substrate includes first and second surfaces and first and second through-holes. The switch is on the first surface and includes first, second and first control terminals. The control circuit is on the first surface and electrically coupled to the first control terminal. The antenna is on the second surface and includes first and second radiation members. The frequency adjustment portion is on the second surface and includes first and second metal portions. The first metal portion includes a first interdigital structure electrically coupled to the first radiation member. The second metal portion includes second and third interdigital structures electrically coupled to the second radiation member. The second and third interdigital structures are electrically coupled to the first and second terminals through the first and second through-holes respectively.Type: GrantFiled: June 5, 2017Date of Patent: August 6, 2019Assignee: Compal Electronics, Inc.Inventors: En-Tsao Chang, Yi-Da Chen, Yi-Hsin Tsai
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Patent number: 10275181Abstract: The invention introduces a method for scheduling and executing commands in a flash memory, performed by a processing unit, including at least the following steps: reading information stored in a command profile space to determine whether a priority command is present in a command queue; de-queuing the priority command from the command queue and executing the priority command when the priority command is present in the command queue; and using a scheduling algorithm to select a simple read/write command from the command queue and executing the simple read/write command when no priority command is present in the command queue.Type: GrantFiled: January 5, 2018Date of Patent: April 30, 2019Assignee: Silicon Motion, Inc.Inventors: Shen-Ting Chiu, Yi-Da Chen
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Publication number: 20190073134Abstract: The invention introduces a method for resetting a flash memory device, performed by a controller of a host, including at least the following steps: driving a memory controller to perform fewer than a maximum number of normal resets after receiving a hardware reset command from a processor; and driving the memory controller to perform a super reset when the normal resets are unsuccessful.Type: ApplicationFiled: March 19, 2018Publication date: March 7, 2019Inventors: Chang-Wei SHEN, Yi-Da CHEN
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Publication number: 20180341430Abstract: The invention introduces a method for scheduling and executing commands in a flash memory, performed by a processing unit, including at least the following steps: reading information stored in a command profile space to determine whether a priority command is present in a command queue; de-queuing the priority command from the command queue and executing the priority command when the priority command is present in the command queue; and using a scheduling algorithm to select a simple read/write command from the command queue and executing the simple read/write command when no priority command is present in the command queue.Type: ApplicationFiled: January 5, 2018Publication date: November 29, 2018Inventors: Shen-Ting Chiu, Yi-Da Chen
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Patent number: 9864001Abstract: An electronic device is provided. The electronic device includes a printed circuit board (PCB), an antenna structure, a radio frequency signal transceiving circuit and a testing structure. The antenna structure is disposed on the PCB. The radio frequency signal transceiving circuit is disposed on the PCB, and is connected to the antenna structure through a conductive line. The testing structure includes a testing point and a grounding structure. The testing point is disposed on the conductive line, and the grounding structure is disposed on the PCB.Type: GrantFiled: June 26, 2015Date of Patent: January 9, 2018Assignee: COMPAL ELECTRONICS, INC.Inventors: Jui-Hung Hsu, Li-Hsin Wang, Ping-Yueh Hsieh, Yi-Da Chen, Jhu-Jyun Chang, Hou-Lung Lin
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Publication number: 20170352955Abstract: A tunable antenna device includes a substrate, a switch, a control circuit, an antenna and a frequency adjustment portion. The substrate includes first and second surfaces and first and second through-holes. The switch is on the first surface and includes first, second and first control terminals. The control circuit is on the first surface and electrically coupled to the first control terminal. The antenna is on the second surface and includes first and second radiation members. The frequency adjustment portion is on the second surface and includes first and second metal portions. The first metal portion includes a first interdigital structure electrically coupled to the first radiation member. The second metal portion includes second and third interdigital structures electrically coupled to the second radiation member. The second and third interdigital structures are electrically coupled to the first and second terminals through the first and second through-holes respectively.Type: ApplicationFiled: June 5, 2017Publication date: December 7, 2017Inventors: En-Tsao Chang, Yi-Da Chen, Yi-Hsin Tsai
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Publication number: 20150377942Abstract: An electronic device is provided. The electronic device includes a printed circuit board (PCB), an antenna structure, a radio frequency signal transceiving circuit and a testing structure. The antenna structure is disposed on the PCB. The radio frequency signal transceiving circuit is disposed on the PCB, and is connected to the antenna structure through a conductive line. The testing structure includes a testing point and a grounding structure. The testing point is disposed on the conductive line, and the grounding structure is disposed on the PCB.Type: ApplicationFiled: June 26, 2015Publication date: December 31, 2015Applicant: COMPAL ELECTRONICS, INC.Inventors: Jui-Hung Hsu, Li-Hsin Wang, Ping-Yueh Hsieh, Yi-Da Chen, Jhu-Jyun Chang, Hou-Lung Lin
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Patent number: 7386353Abstract: A parallel control method for sequential process control flow. First, a parallel step including a plurality of independent sub-steps is generated in a sequential process control flow. One of the sub-steps is directed to execute at a time, and any sub-step gains the right to execute when the other sub-steps are in waiting state. It is assessed the parallel step is complete by whether all of the sub-steps are complete, and the sequential process control flow is controlled to a next step succeeding the parallel step if the parallel step is complete.Type: GrantFiled: April 26, 2004Date of Patent: June 10, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Da Chen, Yao-Hsiung Chang, Dan Ho
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Publication number: 20050240929Abstract: A parallel control method for sequential process control flow. First, a parallel step including a plurality of independent sub-steps is generated in a sequential process control flow. One of the sub-steps is directed to execute at a time, and any sub-step gains the right to execute when the other sub-steps are in waiting state. It is assessed the parallel step is complete by whether all of the sub-steps are complete, and the sequential process control flow is controlled to a next step succeeding the parallel step if the parallel step is complete.Type: ApplicationFiled: April 26, 2004Publication date: October 27, 2005Inventors: Yi-Da Chen, Yao-Hsiung Chang, Dan Ho