Abstract: The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and/or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and/or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

Abstract: The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and/or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and/or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.

Abstract: The present invention provides an ECO method based on adaptive learning applied to ECO operations of netlists in different stages in a chip design process. The method comprises acquiring a first netlist subjected to an ECO in a previous stage and a second netlist to be subjected to an ECO in a current stage; determining a position where the ECO of the previous stage involves netlist modification based on a structural similarity between the first netlist and the second netlist, and delineating an input boundary and an output boundary in the first netlist; searching for, in the second netlist, matching signals matching the input boundary and output boundary delineated in the first netlist; delineating a boundary range of the second netlist to be subjected to the ECO based on the matching signals; and performing the ECO in the delineated boundary range. The method improves efficiency and accuracy of the ECO.

Abstract: The present application provides a method for obtaining an engineering change order (ECO) point based on a comparison of design files, for finding difference ECO points between a revision design and an original design in a chip design, the method includes finding an old GTECH file corresponding to the original design and a new GTECH file corresponding to the revision design; comparing the old GTECH file and the new GTECH file to find key point information; and based on the key point information, analyzing a component composition and connection of a circuit, to find the difference ECO points.

Abstract: A register-transfer level signal mapping construction method and device, wherein the register-transfer level signal mapping construction method comprises: acquiring register-transfer level codes and netlist level codes corresponding to the register-transfer level codes; constructing a circuit according to the register-transfer level codes and the netlist level codes; separating the circuit into a plurality of modules according to syntax of the circuit in a hardware description language; determining a correspondence relationship between the plurality of modules with logic verification methods; acquiring register-transfer level signals of a mapping relationship to be established; and determining netlist level signals corresponding to the register-transfer level codes according to the correspondence relationship between the plurality of modules.

Abstract: A method to transform the function of a programmable circuit (e.g. FPGA) for removing functional bugs or Hardware Trojans is provided.

Abstract: A method to transform the function of a programmable circuit (e.g. FPGA) for removing functional bugs or Hardware Trojans is provided.

Abstract: A method enables arithmetic circuit verification with improved runtime complexity by coupling reverse engineering and a SAT solver together. The method provides a netlist f of a first arithmetic circuit and a netlist g of a second arithmetic circuit; and improves the runtime complexity by conducting equivalence checking between the netlist f and the netlist g such that structural difference between the netlist f and the netlist g is minimized by reverse engineering before generating a conjunctive normal form (CNF) encoding that is solved by a satisfiability (SAT) solver such that the arithmetic circuit verification is completed in polynomial time rather than in exponential time.