Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A computer-implemented method for executing a hot upgrade process is provided. The computer-implemented method includes receiving a process upgrade request during executions of first and second tasks by an old container, determining that the process upgrade request affects the first task but not the second task, labeling the first task but not the second task and acting on the process upgrade request. The computer-implemented method further includes, based on the labeling, storing the first task by the old container and executing the second task by the old container, deleting the old container and instantiating a new container for transformation and execution of the first task.

Abstract: A computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. A multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. An adder circuit is configured to receive the product sum and to provide a partial sum. A partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.

Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: Embodiment described herein provide systems, apparatuses and methods for convoluting a filter (“kernel”) to input data in the form of an input array by reusing computations of repeated data entries in the input array due to convolution movements from one convolution step to the next. In one embodiment, to compute a convolution of an input matrix and a filter matrix, instead of unrolling data entries from the input matrix of each convolution step into an input vector, only non-repeated new data entries at each convolution step may be added to the input vector. An input mapping circuit that implements an input parameter mapping matrix may then iteratively map data entries of the input vector to different weight registers that corresponds to weights in the filter matrix.

Abstract: A computer-implemented method, system and computer program product for identifying a root cause of failures in a CI/CD pipeline. Tags for tasks, templates and/or variables of the operator and the CI/CD pipeline are extracted. Code of the tagged tasks, templates and/or variables of the operator are mapped with the code of the tagged tasks, templates and/or variables of the Cl/CD pipeline forming mappings. Additionally, code of the tagged tasks, templates and/or variables between the roles of the operator are mapped forming mappings. Upon receiving a notification of a failure in the Cl/CD pipeline, a root cause of the failure is identified by searching such mappings for a mapped role or task in relation to the role or task involving the software product which failed in the CI/CD pipeline and searching the log file of the operator for an error in connection with such mapped role or task.

Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.

Abstract: A method, computer program product, and computer system for processing instances of message sequences. Two or more instances are received. Each instance has an instance number and an associated instance Id. Each instance includes a stream of one or more messages. Each message in each stream is associated with a respective task. All messages in the two or more instances whose respective tasks have been completed are distributed into partitions in the broker. Different messages in each instance of at least one instance are distributed into different partitions. The messages distributed in the partitions include parallel task messages. The parallel task messages are sequenced by being grouped by the instance number or instance Id and are sequentially ordered in each group in an ascending order of a timestamp of arrival of each parallel task message at the broker. The parallel task messages in each instance are dispatched to a service.

Abstract: A magnetic assembly includes a magnetic core, a magnetic core set, a circuit board and a positioning plate. The magnetic core set includes a first magnetic member, two second magnetic members and a plurality of third magnetic members. A plurality of separation spaces exist between the first magnetic member and two second magnetic members, and the circuit board is disposed between the magnetic core and the magnetic core set. The positioning plate has a first receptacle configured to receive the first magnetic member, two second receptacles each configured to receive one of the second magnetic members, and a plurality of third receptacles configured to receive the third magnetic members. Therefore, the eddy current loss and the winding loss are reduced, the sizes of the separation spaces are controlled precisely, and the advantages of enhancing the effectiveness of the magnetic assembly are achieved.

Abstract: A coil winding includes a coil. The coil has a first winding segment and a second winding segment. The first winding segment includes a first lead. The second winding segment includes a second lead. The first winding segment is stacked as a first winding portion, and the first lead is connected with the first winding portion. The second winding segment is arranged along a lateral direction as a second winding portion, further arranged on the second winding portion along a lateral direction as a third winding portion, and further arranged on the third winding portion along a lateral direction as a fourth winding portion, and the second lead is connected with the fourth winding portion. Therefore, the space where the first lead located at is directly and sufficiently used, none of any extra space is occupied, hence the space can be effectively utilized.

Abstract: A magnetic component is disclosed. The magnetic component includes a magnetic core assembly, a fastening element, a first winding set and a second winding set. The magnetic core assembly includes at least a pillar. The fastening element is provided on an outer peripheral surface of the pillar. The first winding set is disposed around the outer peripheral surface of the pillar. The second winding set is disposed around the outer peripheral surface of the pillar and engaged with the fastening set. The first winding set and the second winding set are located adjacent to each other and disposed around the outer peripheral surface of the pillar.

Abstract: A magnetic component is disclosed. The magnetic component includes a magnetic core assembly, a fastening element, a first winding set and a second winding set. The magnetic core assembly includes at least a pillar. The fastening element is provided on an outer peripheral surface of the pillar. The first winding set is disposed around the outer peripheral surface of the pillar. The second winding set is disposed around the outer peripheral surface of the pillar and engaged with the fastening set. The first winding set and the second winding set are located adjacent to each other and disposed around the outer peripheral surface of the pillar.

Abstract: A power controlling method for a power supplying system coupled to a load is disclosed. City energy is detected. It is determined whether the city energy corresponds to a first pre-determined condition. When the city energy corresponds to the first pre-determined condition, the city energy is transformed to generate a main power to the load. When the city energy does not correspond to the first pre-determined condition, a fuel cell unit is activated to provide a backup power to the load.

Abstract: A power supply system driving a load including a main power apparatus and a backup power apparatus is disclosed. The main power apparatus provides main power to the load according to city power. The backup power apparatus provides backup power to the load when the city power does not correspond to a first pre-determined condition and includes a recombination unit, a fuel cell unit, a transformation unit, and a control unit. The recombination unit recombines a methanol component to a hydrogen component. The fuel cell unit receives the hydrogen component to generate a first power. The transformation unit detects the city power and transforms the first power to generate the backup power. When the city power does not correspond to a first pre-determined condition, the control unit activates the reformer, the fuel cell unit, and the transformation unit to generate the backup power.

Abstract: A combined structure of hollow bobbin and conductive sheet for a transformer includes a hollow bobbin and at least one conductive sheet. The hollow bobbin includes an outer surface and at least one positioning structure formed on the outer surface. The conductive sheet is fit on the outer surface of the hollow bobbin and includes a main body and at least one engaging structure. The main body has a hollow portion, making the main body to have an inner circumference. The engaging structure is formed on the inner circumference of the main body and is engaged with the positioning structure of the hollow bobbin. The transformer includes at least one winding disposed on the outer surface of the hollow bobbin and abutting against the conductive sheet.

Abstract: A combined structure of hollow bobbin and conductive sheet for a transformer includes a hollow bobbin and at least one conductive sheet. The hollow bobbin includes an outer surface and at least one positioning structure formed on the outer surface. The conductive sheet is fit on the outer surface of the hollow bobbin and includes a main body and at least one engaging structure. The main body has a hollow portion, making the main body to have an inner circumference. The engaging structure is formed on the inner circumference of the main body and is engaged with the positioning structure of the hollow bobbin. The transformer includes at least one winding disposed on the outer surface of the hollow bobbin and abutting against the conductive sheet.