Abstract: A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost.

Abstract: A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost.

Abstract: A chip with a high performance programmable logic system interface, including a first internal device, a second internal device and a bus master, is provided. The first internal device, which is integrated into the chip, communicates with an external device by a first set of internal buses and a first set of external buses. The second internal device, which is integrated into the chip, communicates with the external device by a second set of internal buses and a second set of external buses. The bus master is configured to control the first set of internal buses, the first set of external buses, the second set of internal buses and the second set of external buses. The first internal device and the second internal device communicate with the bus master simultaneously.

Abstract: A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I2C or IIC) and a universal serial bus (USB) for the flexibility of using these interfaces. And, a method for updating firmware of a microcontroller is also provided to utilize each interface more efficiently.

Abstract: A memory accessing system, including an internal memory, an external memory, a microprocessor and a controller, is provided. The internal memory is configured to have a program space with a first address range and a data space with a second address range, and the program space and the data space are for source codes and data storage respectively. The external memory is configured to have an external data space with a third address range for storing data, and the third address range covers the first and second address ranges. The microprocessor is configured to process the source codes and data. The controller is configured to control the access of the program space, data space and the external data space.

Abstract: A method for switching the Num Lock mode of a digital apparatus that is externally coupled with a keypad. When the Num Lock modes of digital apparatus and keypad are different, the keypad transfers the data including a combination code that combines a Num Lock code and a pressed key code to the digital apparatus firstly after any key of the keypad being pressed, and transfers the data including a Num Lock code to the digital apparatus secondly. The main objective of the method according to the present invention is temporally switching Num Lock mode and recovering back to the original mode of the digital apparatus, therefore the input operations of the keypad and the digital apparatus are quite independent and never collision each other.

Abstract: The present invention provides a kind of computer keyboard being able to detect the pressing pressure of keys. The computer keyboard comprises: a plurality of keys; a detecting unit, which outputs a detecting signal according to the pressing pressure of the plurality of keys; and a keyboard controller, which generates a key code according to the detecting signal and sends the key code to a digital device.

Abstract: The present invention provides a kind of computer keyboard being able to detect the pressing pressure of keys. The computer keyboard comprises: a plurality of keys; a detecting unit, which outputs a detecting signal according to the pressing pressure of the plurality of keys; and a keyboard controller, which generates a key code according to the detecting signal and sends the key code to a digital device.

Abstract: A storage apparatus includes: a body; a serial interface connector, which is mounted to the body to connect with a host externally; and a single chip integrated circuit, which is positioned in the body, integrates a storage media and a serial interface, wherein the serial interface connects to the serial interface connector electrically, and the host is able to access the storage media through the serial interface.

Abstract: A high-speed single chip microcomputer compatible with an Intel 8-bits single chip microcomputer, that comprises the feature of: a machine cycle of the high-speed single chip microcomputer containing three state cycles, and the instruction execution time being equal to triple multiple of the state cycle.

Abstract: The present invention provides a method for switching the Num Lock mode of a digital apparatus that is externally coupled with a keypad. When the Num Lock modes of digital apparatus and keypad are different, the keypad transfers the data including a combination code that combines a Num Lock code and a pressed key code to the digital apparatus firstly after any key of the keypad being pressed, and transfers the data including a Num Lock code to the digital apparatus secondly. The main objective of the method according to the present invention is temporally switching Num Lock mode and recovering back to the original mode of the digital apparatus, therefore the input operations of the keypad and the digital apparatus are quite independent and never collision each other.

Abstract: The present invention relates to a parallel variable length decoder and a method for decoding a signed variable length code word. Variable length decoding (VLD) is a widely-used method in data compression, especially, in the applications of image data communication and storage. Many international standards have adopted this technique in video data compression, for example, JPEG, MPEG, CCITT H.261 and so on. Two programmable logic arrays (PLAs) are used in conventional VLD which differ only in there sign. The present invention uses a single PLA which is triggered by bits of signed fixed length inputs, not including a sign bit. The PLA output an unsigned run-level pair. The VLD processes the sign bit outside the PLA. A mask circuit is used to extract the sign bit which is then combined with the decoded unsigned run-level pair to get a signed run-level pair.

Abstract: The present invention is a variable length decoder architecture. A bit-serial variable length decoder (VLD) receives the coded bit stream directly without buffering. The bit serial VLD determines the end of every variable length code word but does not actually decode the code words. The variable length code words are then buffered and decoded by a plurality of VLD's arranged in parallel. High throughout is achieved with a small amount of buffer capacity.

Abstract: A transpose memory is disclosed which has four dual port memories, a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories. If the received matrix is to be outputted to the first type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. If the received matrix is to be outputted to the second type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element.

Abstract: A pipeline multiplier is used for multiplying a multiplicand to a multiplier. The pipeline multiplier includes a plurality of adder stages each adder stage includes a partial product processor for processing a partial product of the multiplicand and one of the multiplier. Each of the adder stages further includes a plurality of ripple carry adder (RCA) bands each band includes a plurality of full adders wherein the carry of the full adders ripple sequentially to the most significant full adder in the RCA band. Furthermore, each of the RCA bands in each adder stage includes approximately same number of full adders. The adder stages are further arranged in sequential order such that each of the RCA bands in each stage are pipelined to a corresponding RCA band, which is a RCA band being more-significantly-shifted by one bit, in next adder stage according to the sequential order whereby an accumulative partial product is propagated from one of the adder stages to a next stage.