Patents by Inventor Yi Feng Lee
Yi Feng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240387511Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Feng CHANG, Jam-Wem LEE
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Publication number: 20240363152Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Inventors: Ku-Feng LIN, Yu-Der CHIH, Yi-Chun SHIH, Chia-Fu LEE
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Publication number: 20240347090Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: ApplicationFiled: April 15, 2024Publication date: October 17, 2024Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
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Patent number: 12080375Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.Type: GrantFiled: August 10, 2023Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ku-Feng Lin, Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee
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Patent number: 12051767Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.Type: GrantFiled: January 20, 2023Date of Patent: July 30, 2024Assignee: EPISTAR CORPORATIONInventors: Yen-Chun Tseng, Kuo-Feng Huang, Shih-Chang Lee, Ming-Ta Chin, Shih-Nan Yen, Cheng-Hsing Chiang, Chia-Hung Lin, Cheng-Long Yeh, Yi-Ching Lee, Jui-Che Sung, Shih-Hao Cheng
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Patent number: 8244500Abstract: A method of adjusting wafer process sequence includes steps of collecting production parameters for a plurality of lots; selecting a plurality of key parameters from the production parameters, wherein the key parameters at least includes a processing sequence; defining a formula to obtain an epsilon value; categorizing the lots into groups according to the epsilon value and the minimum point number by using density-based spatial clustering of application with noise (DBSCAN); and adjusting the processing sequences of the lots in the groups. Thereby, the lots with the same process recipe can be continuously or simultaneously sent into a machine, thereby reducing replacement of process recipes or shortening machine idle time.Type: GrantFiled: June 2, 2009Date of Patent: August 14, 2012Assignee: Inotera Memories, Inc.Inventors: Yun-Zong Tian, Chun Chi Chen, Yi Feng Lee, Wei Jun Chen, Shih Chang Kao, Yij Chieh Chu, Cheng-Hao Chen
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Patent number: 8195431Abstract: A method for evaluating efficacy of prevention maintenance for a tool includes the steps of: choosing a tool which has been maintained preventively and choosing a productive parameter of the tool; collecting values of the productive parameter generated from the tool during a time range for building a varying curve of the productive parameter versus time, modifying the varying curve with a moving average method; transforming the varying curve into a Cumulative Sum chart; and judging whether the values of the productive parameter generated from the tool after the prevention maintenance are more stable, compared with the values of the productive parameter generated from the tool before the prevention maintenance, according to the Cumulative Sum chart. Thereby, if the varying of the values of the productive parameter after the prevention maintenance isn't stable, then the efficacy of this prevention maintenance for the tool is judged not good.Type: GrantFiled: September 25, 2009Date of Patent: June 5, 2012Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Shih Chang Kao, Yun-Zong Tian, Wei Jun Chen
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Patent number: 8170964Abstract: A method for planning a semiconductor manufacturing process based on users' demands includes the steps of: establishing a genetic algorithm model and inputting data; establishing a fuzzy system and setting one output parameter representing percent difference of each cost function in neighbor generations; setting to have a modulation parameter corresponding to each input parameter for adjusting fuzzy sets of the output parameter; executing genetic algorithm actions; executing fuzzy inference actions; eliminating chromosomes that produce output parameter smaller than a defined lower limit, and the remaining chromosomes that produces the largest output parameter is defined as the optimum chromosome, wherein the genetic algorithm actions stops being executed upon the optimum chromosome; then determining whether or not a defined number of generations has been reached, if yes, executing the optimum chromosome of the last generation; if no, continuing executing the genetic algorithm actions, thereby finding the optiType: GrantFiled: May 26, 2009Date of Patent: May 1, 2012Assignee: Inotera Memories, Inc.Inventors: Wei Jun Chen, Chun Chi Chen, Yun-Zong Tian, Yi Feng Lee, Tsung-Wei Lin
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Patent number: 8090668Abstract: A method for predicting cycle time comprises the steps of: collecting a plurality of known sets of data; using a clustering method to classify the known sets of data into a plurality of clusters; using a decision tree method to build a classification rule of the clusters; building a prediction model of each cluster; preparing data predicted set of data; using the classification rule to determine that to which clusters the predicted set of data belongs; and using the prediction model of the cluster to estimate the objective cycle time of the predicted set of data. Therefore, engineers can beforehand know the cycle time that one lot of wafers spend in the forward fabrication process, which helps engineers to properly arrange the following fabrication process of the lot of wafer.Type: GrantFiled: October 1, 2008Date of Patent: January 3, 2012Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Yun-Zong Tian, Tsung-Wei Lin
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Publication number: 20110251708Abstract: A method for planning a production schedule of equipment includes: receiving information about a material replacement of the equipment; and determining a target production schedule of the equipment according to the information about the material replacement of the equipment, wherein the target production schedule includes an idle period, and during the idle period, the equipment stops manufacturing under a normal state.Type: ApplicationFiled: May 19, 2010Publication date: October 13, 2011Inventors: Wei-Jun Chen, Yun-Zong Tian, Yij-Chieh Chu, Yi-Feng Lee
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Patent number: 8032248Abstract: A method for finding the correlation between tool PM (prevention maintenance) and the product yield of the tool is disclosed. The method uses a moving average method to magnify a curve trend that is formed by the product yield data that is captured during a predetermined days before PM and after PM. The magnified curve trend is shown by a Cumulative sum chart. The Cumulative sum chart is analyzed for informing related workers of the effect between the tool PM and the product yield, so as to accurately estimate PM timing. Thereby, via the method, the effect between the tool PM and the product yield may be determined, which serves as an important reference for workers to execute further PM.Type: GrantFiled: July 22, 2009Date of Patent: October 4, 2011Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Yun-Zong Tian, Wei Jun Chen, Tsung-Wei Lin
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Patent number: 8010212Abstract: A method of fuzzy control for adjusting a semiconductor machine comprising: providing measurement values from first the “parameter of a pre-semiconductor manufacturing process”, second the “parameter of the semiconductor manufacturing process”, and third the “operation parameter of the semiconductor manufacturing process”; performing a fuzzy control to define two inputs and one output corresponding to the measurement values, wherein the difference between the first and third values, and the difference between the second and third values, forms the two inputs, then from the two inputs one target output is calculated by fuzzy inference; finally, determining if the target output is in or out of an acceptable range. Whereby the target output is the “machine control parameter of the semiconductor manufacturing process” and when within an acceptable range is used for adjusting the semiconductor machine.Type: GrantFiled: September 30, 2008Date of Patent: August 30, 2011Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Tzu-Cheng Lin, Chun Chi Chen, Yun-Zong Tian
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Publication number: 20110112999Abstract: A method for predicting and warning of WAT value includes the steps as follows. A key process is selected and a WAT value after finishing the key process is used as a predictive goal. A predicting model is built. One batch or plural batches of predictive wafers are prepared, and a Fault Detection and Classification data (FDC data) and a metrology data from the predictive wafers of the key process are collected. The FDC data and the metrology data collected from the predictive wafers are inputted into the predicting model for processing a normal predicting procedure, and a predictive WAT value by the predicting model is outputted. The present invention can accurately predict the WAT value, effectively monitor some specific defective wafers and continuously perform the improvement for the specific defective wafer.Type: ApplicationFiled: February 11, 2010Publication date: May 12, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YI-FENG LEE, SHIH CHANG KAO, YUN-ZONG TIAN, WEI JUN CHEN
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Publication number: 20110010132Abstract: A method for evaluating efficacy of prevention maintenance for a tool includes the steps of: choosing a tool which has been maintained preventively and choosing a productive parameter of the tool; collecting values of the productive parameter generated from the tool during a time range for building a varying curve of the productive parameter versus time, modifying the varying curve with a moving average method; transforming the varying curve into a Cumulative Sum chart; and judging whether the values of the productive parameter generated from the tool after the prevention maintenance are more stable, compared with the values of the productive parameter generated from the tool before the prevention maintenance, according to the Cumulative Sum chart. Thereby, if the varying of the values of the productive parameter after the prevention maintenance isn't stable, then the efficacy of this prevention maintenance for the tool is judged not good.Type: ApplicationFiled: September 25, 2009Publication date: January 13, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YI-FENG LEE, CHUN-CHI CHEN, SHIH-CHANG KAO, YUN-ZONG TIAN, WEI-JUN CHEN
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Patent number: 7855086Abstract: A method for monitoring fabrication parameters comprises steps of: obtaining a normal parameter variance curve and a comparing parameter variance curve; defining a plurality of normal parameter points on the normal parameter variance curve; defining a plurality of comparing parameter points on the comparing parameter variance curve; finding out the corresponding comparing parameter points nearest to the normal parameter points; calculating the distances between the normal parameter points and the corresponding comparing parameter points thereof; summing up the distances so as to receive a total distance; and determining whether or not the total distance exceeds a limit. Via this arrangement, when fabrication parameter of tool is abnormal, it can be efficiently and immediately determined.Type: GrantFiled: May 20, 2009Date of Patent: December 21, 2010Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Yun-Zong Tian, Wei Jun Chen
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Publication number: 20100256792Abstract: A method of adjusting wafer process sequence includes steps of collecting production parameters for a plurality of lots; selecting a plurality of key parameters from the production parameters, wherein the key parameters at least includes a processing sequence; defining a formula to obtain an epsilon value; categorizing the lots into groups according to the epsilon value and the minimum point number by using density-based spatial clustering of application with noise (DBSCAN); and adjusting the processing sequences of the lots in the groups. Thereby, the lots with the same process recipe can be continuously or simultaneously sent into a machine, thereby reducing replacement of process recipes or shortening machine idle time.Type: ApplicationFiled: June 2, 2009Publication date: October 7, 2010Applicant: INOTERA MEMORIES, INC.Inventors: YUN-ZONG TIAN, CHUN CHI CHEN, YI FENG LEE, WEI JUN CHEN, SHIH CHANG KAO, YIJ CHIEH CHU, CHENG-HAO CHEN
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Publication number: 20100233830Abstract: A method for monitoring fabrication parameters comprises steps of: obtaining a normal parameter variance curve and a comparing parameter variance curve; defining a plurality of normal parameter points on the normal parameter variance curve; defining a plurality of comparing parameter points on the comparing parameter variance curve; finding out the corresponding comparing parameter points nearest to the normal parameter points; calculating the distances between the normal parameter points and the corresponding comparing parameter points thereof; summing up the distances so as to receive a total distance; and determining whether or not the total distance exceeds a limit. Via this arrangement, when fabrication parameter of tool is abnormal, it can be efficiently and immediately determined.Type: ApplicationFiled: May 20, 2009Publication date: September 16, 2010Applicant: INOTERA MEMORIES, INC.Inventors: YI FENG LEE, CHUN CHI CHEN, YUN-ZONG TIAN, WEI JUN CHEN
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Publication number: 20100234978Abstract: A method for finding the correlation between tool PM (prevention maintenance) and the product yield of the tool is disclosed. The method uses a moving average method to magnify a curve trend that is formed by the product yield data that is captured during a predetermined days before PM and after PM. The magnified curve trend is shown by a Cumulative sum chart. The Cumulative sum chart is analyzed for informing related workers of the effect between the tool PM and the product yield, so as to accurately estimate PM timing. Thereby, via the method, the effect between the tool PM and the product yield may be determined, which serves as an important reference for workers to execute further PM.Type: ApplicationFiled: July 22, 2009Publication date: September 16, 2010Inventors: YI FENG LEE, Chun Chi Chen, Yun-Zong Tian, Wei Jun Chen, Tsung-Wei Lin
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Publication number: 20100205127Abstract: A method for planning a semiconductor manufacturing process based on users' demands includes the steps of: establishing a genetic algorithm model and inputting data; establishing a fuzzy system and setting one output parameter representing percent difference of each cost function in neighbor generations; setting to have a modulation parameter corresponding to each input parameter for adjusting fuzzy sets of the output parameter; executing genetic algorithm actions; executing fuzzy inference actions; eliminating chromosomes that produce output parameter smaller than a defined lower limit, and the remaining chromosomes that produces the largest output parameter is defined as the optimum chromosome, wherein the genetic algorithm actions stops being executed upon the optimum chromosome; then determining whether or not a defined number of generations has been reached, if yes, executing the optimum chromosome of the last generation; if no, continuing executing the genetic algorithm actions, thereby finding the optiType: ApplicationFiled: May 26, 2009Publication date: August 12, 2010Applicant: INOTERA MEMORIES, INC.Inventors: WEI JUN CHEN, CHUN CHI CHEN, YUN-ZONG TIAN, YI FENG LEE, TSUNG-WEI LIN
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Publication number: 20100010763Abstract: A method of detecting variance by regression model is disclosed. Said method comprising: preparing the FDC and WAT data for analysis, figuring out what latent variable effect WAT by Factor Analysis, utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components, demonstrating how the tool and FDC affect WAT by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.Type: ApplicationFiled: September 2, 2008Publication date: January 14, 2010Applicant: INOTERA MEMORIES INC.Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, YI FENG LEE