Patents by Inventor Yi Gyeong Kim
Yi Gyeong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250172657Abstract: A radar device that detects a detection target includes a receiver that receives an echo pulse reflected from the detection target and a radar control block that controls the radar device. The receiver includes a low-noise amplifying module that amplifies the echo pulse and a high-speed sampling module that samples a receive signal generated as the low-noise amplifying module amplifies the echo pulse. The high-speed sampling module includes a comparison reference signal generation circuit that generates comparison reference signals including a first comparison reference signal and a second comparison reference signal, a first comparison circuit that compares the receive signal with the first comparison reference signal to generate a first comparison signal, and a second comparison circuit that compares the receive signal with the second comparison reference signal. The first comparison reference signal is greater in level than the second comparison reference signal.Type: ApplicationFiled: October 16, 2024Publication date: May 29, 2025Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Min-Hyung CHO, Yi-Gyeong KIM, Kyung Hwan PARK, Young-deuk JEON
-
Publication number: 20250157499Abstract: Disclosed herein is a reference voltage calibration apparatus in a memory interface. The reference voltage calibration apparatus includes a first low-pass filter configured to receive a clock signal, a second low-pass filter configured to receive an inverted clock signal that is an inverted signal of the clock signal, a first comparator configured to compare an output of the first low-pass filter with a reference voltage, a second comparator configured to compare an output of the second low-pass filter with the reference voltage, an up/down counter configured to count upward or downward from output values of the first comparator and the second comparator, respectively, and a digital-to-analog converter configured to convert an up/down counter value into an analog signal, and then output the reference voltage, wherein the digital-to-analog converter applies a calibration voltage based on the reference voltage to the first low-pass filter and to the second low-pass filter.Type: ApplicationFiled: August 30, 2024Publication date: May 15, 2025Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Young-Deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO
-
Publication number: 20250078880Abstract: An apparatus for correcting output impedance of a memory interface driving circuit, the apparatus comprising: a first PD driver including a plurality of first sub PD drivers connected to each other in parallel; a first control unit configured to sequentially change a first control code, the first control code being a combination of control signals for turning the plurality of first sub PD drivers on or off in each pull-down sweep; and a first comparator configured to generate a first output pattern, the first output pattern being a sequence of 0 or 1 representing a result of comparing an output voltage of the first PD driver generated according to the first control code with a first reference voltage, wherein the first control unit determines a first impedance correction code for the memory interface driving circuit from among the sequentially changing first control codes using the first output pattern.Type: ApplicationFiled: September 5, 2024Publication date: March 6, 2025Applicant: Electronics and Telecommunications Research InstituteInventors: Min Hyung CHO, Yi Gyeong KIM, Young Deuk JEON, Young Su KWONG, Su Jin PARK
-
Publication number: 20250067841Abstract: Disclosed is an ultra-wide band (UWB) radar device including a first antenna circuit including a first transmission circuit, a first reception circuit, a first oscillator that supplies a first clock signal to the first transmission circuit and the first reception circuit, and a first frequency counter, a second antenna circuit including a second transmission circuit, a second reception circuit, a second oscillator that supplies a second clock signal to the second transmission circuit and the second reception circuit, and a second frequency counter, and a controller that detects the target. The controller corrects a frequency error between the first clock signal and the second clock signal and compensates for a synchronization error between the first antenna circuit and the second antenna circuit.Type: ApplicationFiled: June 4, 2024Publication date: February 27, 2025Applicant: Electronics and telecommunications Research InstituteInventors: Yi-Gyeong KIM, Kyung Hwan Park, Sujin Park, Young-deuk Jeon, Min-Hyung Cho
-
Patent number: 12231100Abstract: An apparatus for receiving a strobe signal may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.Type: GrantFiled: September 6, 2022Date of Patent: February 18, 2025Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Yi-Gyeong Kim, Young-Deuk Jeon, Young-Su Kwon, Jin-Ho Han
-
Publication number: 20250052860Abstract: Disclosed is a receiver of a radar device, which includes a sampling circuit that receives a reflected pulse signal having a first period reflected from a detection target and samples the reflected pulse signal as a first received signal in response to a clock signal having a second period equal to the first period, an integration circuit that, in response to the clock signal, generates an analog integration signal based on the first received signal and a control signal, a comparison circuit that, in response to the clock signal, adjusts a count value and the control signal based on a result of comparing the analog integration signal with a reference signal and outputs the control signal to the integration circuit, and an ADC circuit that converts the analog integration signal into a digital integration signal.Type: ApplicationFiled: July 30, 2024Publication date: February 13, 2025Inventors: Young-deuk JEON, Yi-Gyeong KIM, Kyung Hwan PARK, Sujin PARK, MIN-HYUNG CHO
-
Patent number: 12206420Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.Type: GrantFiled: July 18, 2023Date of Patent: January 21, 2025Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Yi-Gyeong Kim, Young-Su Kwon, Su-Jin Park, Young-Deuk Jeon, Min-Hyung Cho, Jae-Woong Choi
-
Publication number: 20240195399Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.Type: ApplicationFiled: July 18, 2023Publication date: June 13, 2024Inventors: Yi-Gyeong KIM, Young-Su KWON, Su-Jin PARK, Young-Deuk JEON, Min-Hyung CHO, Jae-Woong CHOI
-
Publication number: 20240194241Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.Type: ApplicationFiled: July 18, 2023Publication date: June 13, 2024Inventors: Young-Deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
-
Publication number: 20240195400Abstract: Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.Type: ApplicationFiled: August 23, 2023Publication date: June 13, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Min-Hyung CHO, Yi-Gyeong KIM, Su-Jin PARK, Young-Deuk JEON
-
Publication number: 20240163139Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.Type: ApplicationFiled: November 10, 2023Publication date: May 16, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Young-deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
-
Publication number: 20230115549Abstract: Disclosed herein is an apparatus for receiving a strobe signal. The apparatus may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.Type: ApplicationFiled: September 6, 2022Publication date: April 13, 2023Inventors: Yi-Gyeong KIM, Young-deuk JEON, Young-Su KWON, Jin-Ho HAN
-
Patent number: 10663974Abstract: Provided are an object recognition device, an autonomous driving system including the same, and an object recognition method using the object recognition device. The object recognition device includes an object frame information generation unit, a frame analysis unit, an object priority calculator, a frame complexity calculator, and a mode control unit. The object frame information generation unit generates object frame information based on a mode control signal. The frame analysis unit generates object tracking information based on object frame information. The object priority calculator generates based on object tracking information. The frame complexity calculator generates a frame complexity based on object tracking information. The mode control unit generates a mode control signal for adjusting an object recognition range and a calculation amount of the object frame information generation unit based on the priority information, the frame complexity, and the resource occupation state.Type: GrantFiled: November 6, 2017Date of Patent: May 26, 2020Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jung Hee Suk, Yi-Gyeong Kim, Chun-Gi Lyuh, Young-Deuk Jeon, Min-Hyung Cho
-
Patent number: 10644668Abstract: A resonator-based sensor and a sensing method thereof for sensing a change in a material that is subject to be sensed which include: generating an oscillation voltage signal by amplifying a current signal output from a resonator in accordance with a physical-chemical change of the material; and generating a gain control signal corresponding to a motional resistance and a clock signal corresponding to a resonant frequency of the resonator are provided.Type: GrantFiled: September 20, 2018Date of Patent: May 5, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Hyunjoong Lee, Yi-Gyeong Kim, Yil Suk Yang, Woo Seok Yang, Chang Han Je
-
Publication number: 20190319599Abstract: A resonator-based sensor and a sensing method thereof for sensing a change in a material that is subject to be sensed which include: generating an oscillation voltage signal by amplifying a current signal output from a resonator in accordance with a physical-chemical change of the material; and generating a gain control signal corresponding to a motional resistance and a clock signal corresponding to a resonant frequency of the resonator are provided.Type: ApplicationFiled: September 20, 2018Publication date: October 17, 2019Inventors: Hyunjoong Lee, Yi-Gyeong Kim, Yil Suk Yang, Woo Seok Yang, Chang Han Je
-
Publication number: 20190293746Abstract: Provided is an electronic device including a first microphone array including a plurality of microphones configured to generate first signals related to a first sound in response to the first sound from a sound source, and a processor configured to generate a first result related to a first direction to the sound source from a first reference position among first positions at which the first sound is received by the plurality of microphones based on second signals corresponding to a second sound received from the sound source at second positions separated from the first positions and the first signals, and generate a second result related to a distance to the sound source based on information on a second direction from a second reference position among the second positions to the sound source and the first result.Type: ApplicationFiled: January 31, 2019Publication date: September 26, 2019Applicant: ELECTRONICS AND TELECOMUNICATIONS RESEARCH INSTITUTEInventors: Sung Q LEE, Kang-Ho PARK, Yi-Gyeong KIM
-
Patent number: 10396740Abstract: The present disclosure relates to a microphone driving device and a digital microphone including the same. A microphone driving device according to an embodiment of the inventive concept includes a voltage-to-current converter, a current-to-voltage converter, an analog-to-digital converter, a digital amplification unit, and a gain controller. The voltage-to-current converter converts an acoustic signal to an output current signal based on a gain control signal. The current-to-voltage converter converts the output current signal to an amplified voltage signal. The analog-to-digital converter converts the amplified voltage signal to a digital signal. The digital amplification unit amplifies the digital signal to an amplified digital signal based on the gain control signal. The gain controller generates a gain control signal. The microphone driving device and the digital microphone including the same according to the inventive concept may have a wide dynamic range and reduce the influence of noise.Type: GrantFiled: August 23, 2017Date of Patent: August 27, 2019Assignee: ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Yi-Gyeong Kim, Woo Seok Yang, Min-Hyung Cho
-
Patent number: 10154225Abstract: The present disclosure relates to a frame grabber, an image processing system, and an image processing method. A frame grabber according to an embodiment of the inventive concept includes a plurality of decoders, a plurality of image controllers, a plurality of memories, a synchronization controller, and a synchronization memory. The plurality of decoders generate a plurality of image data by decoding a plurality of image signals. The plurality of image controllers generate a plurality of pixel data and a plurality of frame information data on the basis of the plurality of image data. The plurality of memories store the plurality of pixel data. The synchronization controller receives the plurality of frame information data, and generates synchronization data on the basis of the plurality of frame information data. The synchronization memory stores the frame information data and the synchronization data.Type: GrantFiled: July 18, 2017Date of Patent: December 11, 2018Assignee: ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chun-Gi Lyuh, Yi-Gyeong Kim, Jung Hee Suk, Young-Deuk Jeon, Min-Hyung Cho
-
Publication number: 20180143646Abstract: Provided are an object recognition device, an autonomous driving system including the same, and an object recognition method using the object recognition device. The object recognition device includes an object frame information generation unit, a frame analysis unit, an object priority calculator, a frame complexity calculator, and a mode control unit. The object frame information generation unit generates object frame information based on a mode control signal. The frame analysis unit generates object tracking information based on object frame information. The object priority calculator generates based on object tracking information. The frame complexity calculator generates a frame complexity based on object tracking information. The mode control unit generates a mode control signal for adjusting an object recognition range and a calculation amount of the object frame information generation unit based on the priority information, the frame complexity, and the resource occupation state.Type: ApplicationFiled: November 6, 2017Publication date: May 24, 2018Inventors: Jung Hee SUK, Yi-Gyeong KIM, Chun-Gi LYUH, Young-Deuk JEON, Min-Hyung CHO
-
Publication number: 20180146155Abstract: The present disclosure relates to a frame grabber, an image processing system, and an image processing method. A frame grabber according to an embodiment of the inventive concept includes a plurality of decoders, a plurality of image controllers, a plurality of memories, a synchronization controller, and a synchronization memory. The plurality of decoders generate a plurality of image data by decoding a plurality of image signals. The plurality of image controllers generate a plurality of pixel data and a plurality of frame information data on the basis of the plurality of image data. The plurality of memories store the plurality of pixel data. The synchronization controller receives the plurality of frame information data, and generates synchronization data on the basis of the plurality of frame information data. The synchronization memory stores the frame information data and the synchronization data.Type: ApplicationFiled: July 18, 2017Publication date: May 24, 2018Inventors: Chun-Gi LYUH, Yi-Gyeong KIM, Jung Hee SUK, Young-Deuk JEON, Min-Hyung CHO