Abstract: The present invention provides a power amplifier system configured to receive an input audio signal to generate an output audio signal is disclosed. The power amplifier system includes a reference signal generator, a dynamic headroom generator and a DC-DC converter. The reference signal generator is configured to generate a reference signal according to the input signal. The dynamic headroom generator is configured to generate an output reference signal according to the reference signal and a change rate of a signal, wherein the signal is the reference signal, the input audio signal, or correlated with the reference signal or the input audio signal. The DC-DC converter is configured to generate a supply voltage to a power amplifier, wherein a voltage level of the supply voltage is determined according to the output reference signal, and the power amplifier is configured to generate the output audio signal according to the input audio signal.

Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

Abstract: A polar code decoding apparatus and an operation method thereof are provided. The polar code decoding apparatus includes a path expanding circuit and a node processing circuit. The path expanding circuit expands each of multiple previous paths corresponding to multiple previous decoding results into multiple candidate paths according to a current node. The path expanding circuit dynamically determines a path expanding number of the candidate paths of each of the previous paths according to an unreliable information bit number of the current node. The node processing circuit performs a path competition operation to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results.

Abstract: The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.