Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ?k values is provided. A set of VBi values (i=1 to M, M?3) is provided. A set of RSDi,j (i=1 to M?1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq_q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ?k, with an iteration method. The ?k value making the set of RSDi,j values or Vtq_q,j values closest to each other is determined as an accurate ?k value. The mean value of RSDi,j at the accurate ?k value is calculated as an accurate RSD value.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ?k values is provided. A set of VBi values (i=1 to M, M?3) is provided. A set of RSDi,j (i=1 to M?1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq—q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ?k, with an iteration method. The ?k value making the set of RSDi,j values or Vtq—q,j values closest to each other is determined as an accurate ?k value. The mean value of RSDi,j at the accurate ?k value is calculated as an accurate RSD value.

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.