Patents by Inventor Yi-Hao Chien

Yi-Hao Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018140
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 25, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yi-Hao Chien, Kazuaki Takesako, Kai Jen, Hung-Yu Wei
  • Publication number: 20210013104
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate stack disposed over the semiconductor substrate, a first oxide spacer disposed along a sidewall of the gate stack, a protection portion disposed over the first oxide spacer, and an interlayer dielectric layer disposed over the semiconductor substrate. The first oxide spacer and the protection portion are disposed between the gate stack and the interlayer dielectric layer.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Kai JEN, Li-Ting WANG, Yi-Hao CHIEN
  • Publication number: 20200365597
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, bit lines disposed on the dielectric layer, spacers and a contact. The substrate has active areas arranged in parallel with each other. The bit lines are arranged in parallel with each other. Each bit line is partially overlapped with the corresponding active area. Each bit line has first portions and second portions arranged alternately in an extending direction thereof, and a width of the first portions is smaller than that of the second portions. The spacers are disposed on the sidewalls of each bit line. The contact is disposed between the adjacent bit lines and adjacent to the corresponding first portion of at least one of the adjacent bit lines, penetrates through the dielectric layer, and is in contact with the corresponding active area.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 19, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Chih Hsu, Yi-Hao Chien, Huang-Nan Chen
  • Publication number: 20200335506
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 22, 2020
    Inventors: Yi-Hao CHIEN, Kazuaki TAKESAKO, Kai JEN, Hung-Yu WEI
  • Publication number: 20200185495
    Abstract: A semiconductor device is provided, including a substrate; a dielectric structure over the substrate; and a capping layer over the dielectric structure. The bottom of the capping layer has an M-shaped cross section. The capping layer and the dielectric structure are formed of different materials.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Chien-Hsu TSENG, Chia-Lan HSU, Kai JEN, Yi-Hao CHIEN
  • Patent number: 9613967
    Abstract: A method of fabricating a memory device includes providing a substrate having a first region and a second region. A first dielectric layer is formed on the substrate in the first region. A conductive layer is formed on the substrate in the second region. A top surface of the conductive layer is lower than a top surface of the first dielectric layer. A second dielectric layer is formed on the substrate. A portion of the second dielectric layer and a portion of the conductive layer are removed to form a first opening in the conductive layer and the second dielectric layer in the second region. The first opening exposes a surface of the substrate. A portion of the substrate in the second region is removed to form a trench in the substrate in the second region. A third dielectric layer is formed in the trench and the first opening.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 4, 2017
    Assignee: Winbond Electronics Corp.
    Inventors: Yi-Hao Chien, Yoshinori Tanaka, Wei-Che Chang