Abstract: A method of optimizing the exposure times of regions of pixels of an image sensor array during exposure is accomplished by utilizing time interval sampling of an image sensor array comprising of pixels configured to generate digital image signals. Luminance values are extracted from each digital image signal and analyzed to determine if a pixel has reached the optimal exposure. If a pixel has reached the optimal exposure, subsequent digital image signals from this pixel will not be recorded. This preserves the recording of the optimal digital image signal generated by the pixel at the time when the pixel reached its optimal exposure. This process of selectively terminating the recording of digital image signals based on optimal exposures of the pixels can be performed on individual pixels or can be performed on a region of pixels.

Abstract: Photo-sensors, such as photo-diodes, are formed using regions with cross-sections that increase the overall quantum efficiency of the resulting photo-sensor. The cross-sections have additional (e.g., interior) side-wall interfaces, and, in some embodiments, an additional, relatively shallow bottom interface. The increased total side-wall area and any additional shallow bottom area increase the total photo-junction volume located near the surface of the device. As a result, a greater fraction of photons having relatively small absorption lengths (e.g., blue light) will be absorbed within a photo-junction, thereby increasing the quantum efficiency for those photons. The present invention enables photo-sensors to be implemented with more uniform spectral response.

Abstract: Photo-sensors, such as photo-diodes, are formed using regions having layout shapes that tend to decrease leakage associated with high electric field strengths and mechanical stresses along the region's non-horizontal edges. According to one characterization of the present invention, the regions have a layout shape having more than four sides, in which all interior angles between adjacent sides of the layout shape are greater than 90 degrees. According to another characterization, the regions have a layout shape having at least one pair of mutually orthogonal sides with an intervening side that forms two interior angles greater than 90 degrees with the mutually orthogonal sides. Under either characterization, the electric field strengths and the mechanical stresses along the non-horizontal edges of the region defined by the adjacent sides of the layout shape, are reduced, thereby reducing leakage and increasing the overall quantum efficiency of the resulting photo-sensors.

Abstract: Improved conductive pads and conductive lines for use on integrated circuit chips include one or more conductive layers having a wider width than convention conductive lines for improved current and power carrying capacity. A layer of insulating and shock resistant is included over said layers of wider width, and additional pads can be formed on said layer of insulating and shock resistant material. Additional improved conductive pads are formed on the integrated circuit chip over a region containing a conductive line. The improved pads and conductive lines provide high power and current carrying capacity, and simultaneously allow for high pad density on an integrated circuit chip. Said pads and conductive lines can include a layer of metal which is electrically insulated using upper and lower layers of insulating material, with this layer of metal providing shock resistance particularly to such lower layer of insulating material.

Abstract: The present invention provides a bipolar transistor in which a lightly doped n-type hot-carrier shield extends in an epitaxial layer adjacent from a poly-emitter to an extrinsic base. This hot-carrier shield minimizes performance impairment that would otherwise occur due to a hot-carrier effect. Key steps in the method of making the bipolar transistor include a differential thermal oxidation while the poly-emitter is covered with a nitride cap. After the nitride cap is removed, an n-type dopant is implanted. The unprotected poly emitter is heavily doped. The implant partially penetrates a relatively thin oxide growth, thereby forming the hot-carrier shield. Other areas, such as the extrinsic base, and a polycrystalline base extension are covered by a relatively thick oxide growth and are unaffected by the n-type implant.

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: Gate oxide on a semiconductor wafer is effectively stressed on a per-wafer basis during fabrication. Because it was effectively stressed, gross testing the gate oxide after device fabrication provides a good indication whether a completed MOS device will be subject to infant mortality. After the gate oxide is formed, a source of overvoltage may be coupled between the raw oxide and the underside of the wafer, to accelerate stress due to defects in the oxide. Alternatively, the oxide may be stressed after deposition of the gate material by coupling a source of overvoltage directly to the gate material and to a probe on the underside of the wafer. The oxide may also be stressed after patterning and definition of the gate material by coupling a source of over-voltage to all of the gates simultaneously, preferably using a mercury probe, plasma or a conductive conforming membrane, and to a probe on the underside of the wafer.

Abstract: The present invention provides a BiCMOS integrated circuit with bipolar, NMOS and PMOS transistors. In a bipolar transistor, an emitter buffer is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link. However, the n-type dopant is implant using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section. Local interconnects are formed using a "dual-gate" technique, in which a tungsten silicide cap layer is formed over polysilicon to short pn junctions in the interconnect.

Abstract: A circuit protects the series coupled PMOS-NMOS transistor output stage, input stage or input/output stage commonly found in a CMOS device from output pad ESD, whether or not the CMOS device is mounted in a circuit board or coupled to a power source. The circuit includes a second PMOS transistor whose output leads are coupled between the output pad and the gate of the output NMOS transistor, and also includes a resistor coupled between the gate of this second PMOS transistor and a voltage source node. A positive potential ESD at the output pad will turn on the second PMOS transistor, thereby coupling positive ESD potential to the gate of the output NMOS transistor. This causes the output NMOS transistor to turn on, avoiding the "snapback" mode destruction that would occur if the second PMOS transistor were not present.